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PDF ADV478 Data sheet ( Hoja de datos )

Número de pieza ADV478
Descripción CMOS 80 MHz Monolithic 256 x 24(18) Color Palette RAM-DACs
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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a
CMOS 80 MHz Monolithic 256 ؋ 24(18)
Color Palette RAM-DACs
ADV478/ADV471
FEATURES
Personal System/2* Compatible
FUNCTIONAL BLOCK DIAGRAM
80 MHz Pipelined Operation
Triple 8-Bit (6-Bit) D/A Converters
256 ؋ 24(18) Color Palette RAM
15 ؋ 24(18) Overlay Registers
RS-343A/RS-170 Compatible Outputs
Sync on All Three Channels
Programmable Pedestal (0 or 7.5 IRE)
External Voltage or Current Reference
Standard MPU Interface
+5 V CMOS Monolithic Construction
44-Pin PLCC Package
Power Dissipation: 800 mW
OAPPLICATIONS
BHigh Resolution Color Graphics
SCAE/CAD/CAM Applications
Image Processing
OInstrumentation
Desktop Publishing
LAVAILABLE CLOCK RATES
E80 MHz
T66 MHz
E50 MHz
35 MHz
GENERAL DESCRIPTION
The ADV478 (ADV®) and ADV471 are pin compatible and
software compatible RAM-DACs designed specifically for
Personal System/2 compatible color graphics.
The ADV478 has a 256 × 24 color lookup table with triple 8-bit
video D/A converters. It may be configured for either 6 bits or
8 bits per color operation. The ADV471 has a 256 × 18 color
lookup table with triple 6-bit video D/A converters.
Options on both parts include a programmable pedestal (0 or
7.5 IRE) and use of an external voltage or current reference.
ADV is a registered trademark of Analog Devices, Inc.
*Personal System/2 is a trademark of International Business Machines Corp.
Fifteen overlay registers provide for overlaying cursors, grids,
menus, EGA emulation, etc. Also supported is a pixel read
mask register and sync generation on all three channels.
The ADV478 and ADV471 generate RS-343A compatible
video signals into a doubly terminated 75 load, and RS-170
compatible video signals into a singly terminated 75 load,
without requiring external buffering. Differential and integral
linearity errors are guaranteed to be a maximum of ± 1 LSB for
the ADV478 and ± 1/4 LSB for the ADV471 over the full tem-
perature range.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703

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ADV478 pdf
ADV478/ADV471
PIN FUNCTION DESCRIPTION
Pin
Mnemonic
Function
BLANK
Composite blank control input (TTL compatible). A logic zero drives the analog outputs to the blanking level as
illustrated in Tables IV and V. It is latched on the rising edge of CLOCK. When BLANK is a logical zero, the
pixel and overlay inputs are ignored
SETUP
Setup control input. Used to specify either a 0 IRE (SETUP = GND) or 7.5 IRE (SETUP = VAA) blanking
pedestal.
SYNC
Composite sync control input (TTL compatible). A logical zero on this input switches off a 40 IRE current source
on the analog outputs (see Figures 3 and 4). SYNC does not override any other control or data input, as shown in
Tables IV and V; therefore, it should be asserted only during the blanking interval. It is latched on the rising edge
CLOCK
P0–P7
OBOL0–OL3
SOIOR, IOG, IOB
LETEIREF
of CLOCK.
Clock input (TTL compatible). The rising edge of CLOCK latches the P0–P7, OL0–OL3, SYNC, and BLANK
inputs. It is typically the pixel clock rate of the video system. It is recommended that CLOCK be driven by a dedi-
cated TTL buffer.
Pixel select inputs (TTL compatible). These inputs specify, on a pixel basis, which one of the 256 entries in the
color palette RAM is to be used to provide color information. They are latched on the rising edge of CLOCK. P0
is the LSB. Unused inputs should be connected to GND.
Overlay select inputs (TTL compatible). These inputs specify which palette is to be used to provide color informa-
tion, as illustrated in Table III. When accessing the overlay palette, the P0–P7 inputs are ignored. They are
latched on the rising edge of CLOCK. OL0 is the LSB. Unused inputs should be connected to GND.
Red, green, and blue current outputs. These high impedance current sources are capable of directly driving a
doubly terminated 75 coaxial cable (Figures 5 and 6).
Full-scale adjust control. Note that the IRE relationships in Figures 3 and 4 are maintained, regardless of the
full-scale output current.
When using an external voltage reference (Figure 5), a resistor (RSET) connected between this pin and GND
controls the magnitude of the full-scale video signal. The relationship between RSET and the full-scale output
current on each output is:
RSET () = K × 1,000 × VREF (V)/IOUT (mA)
K is defined in the table below, along with corresponding RSET values for doubly terminated 75 loads.
When using an external current reference (Figure 6), the relationship between IREF and the full-scale output
current on each output is:
IREF (mA) = IOUT (mA)/K
Mode
6-Bit
8-Bit
6-Bit
8-Bit
Pedestal
7.5 IRE
7.5 IRE
0 IRE
0 IRE
K
3.170
3.195
3.000
3.025
RSET ()
147
147
147
147
COMP
VREF
OPA
VAA
GND
WR
Compensation pin. If an external voltage reference is used (Figure 5), this pin should be connected to OPA. If an
external current reference is used, this pin should be connected to IREF. A 0.1 µF ceramic capacitor must always be
used to bypass this pin to VAA.
Voltage reference input. If an external voltage reference is used (Figure 5), it must supply this input with a 1.2 V
(typical) reference. If an external current reference is used (Figure 6), this pin should be left floating, except for
the bypass capacitor. A 0.1 µF ceramic capacitor must always be used to decouple this input to VAA as shown in
Figures 5 and 6.
Reference amplifier output. If an external voltage reference is used (Figure 5), this pin must be connected to
COMP. When using an external current reference (Figure 6), this pin should be left floating.
Analog power. All VAA pins must be connected to the Analog Power Plane.
Analog ground. All GND pins must be connected to the Ground Plane.
Write control input (TTL compatible). D0–D7 data is latched on the rising edge of WR, and RS0–RS2 are
latched on the falling edge of WR during MPU write operations. See Figure 1.
REV. B
–5–

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ADV478 arduino
ADV478/ADV471
Digital Signal Interconnect
The digital inputs to the ADV478/ADV471 should be isolated
as much as possible from the analog outputs and other analog
circuitry. Also, these input signals should not overlay the analog
power plane.
Due to the high clock rates involved, long clock lines to the
ADV478/ADV471 should be avoided to reduce noise pickup.
Analog Signal Interconnect
The ADV478/ADV471 should be located as close as possible to
the output connectors to minimize noise pickup and reflections
due to impedance mismatch.
The video output signals should overlay the ground plane, and
not the analog power plane, to maximize the high frequency
power supply rejection.
Any active termination resistors for the digital inputs should be
connected to the regular PCB power plane (VCC), and not the
analog power plane.
For maximum performance, the analog outputs should each
have a 75 load resistor connected to GND. The connection
between the current output and GND should be as close as pos-
sible to the ADV478/ADV471 to minimize reflections.
NOTE: Additional information on PC Board layout can be
OBSOLETEobtained in an application note entitled “Design and Layout of
a Video Graphics System for Reduced EMI” from Analog
Devices (Publication Note E1309–15–10/89).
Figure 6. Typical Connection Diagram and Component List (External Current Reference)
APPLICATION INFORMATION
EXTERNAL VOLTAGE VS. CURRENT REFERENCE
The ADV478/ADV471 is designed to have excellent perfor-
mance using either an external voltage or current reference.
The voltage reference design (Figure 5) has the advantages of
temperature compensation, simplicity, lower cost and provides
excellent power supply rejection. The current reference design
(Figure 6) requires more components to provide adequate
power supply rejection and temperature compensation (two
transistors, three resistors and additional capacitors).
RS-170 Video Generation
For generation of RS-170 compatible video, it is recommended
that the DAC outputs be connected to a singly terminated 75
load. If the ADV478/ADV471 is not driving a large capacitive
load, there will be negligible difference in video quality between
doubly terminated 75 and singly terminated 75 loads.
If driving a large capacitive load (load RC> 1/(2 π fC)), it is rec-
ommended that an output buffer (such as an AD848 or
AD9617 with an unloaded gain>2) be used to drive a doubly
terminated 75 load.
REV. B
–11–

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