PDF ADV473 Data sheet ( Hoja de datos )

Número de pieza	ADV473
Descripción	CMOS 135 MHz True-Color Graphics Triple 8-Bit Video RAM-DAC
Fabricantes	Analog Devices
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No Preview Available ! a CMOS 135 MHz True-Color Graphics Triple 8-Bit Video RAM-DAC ADV473 FEATURES ADV478/ADV471 (ADV®) Register Level Compatible IBM PS/2,* VGA/XGA Compatible 135 MHz Pipelined Operation Triple 8-Bit D/A Converters Triple 256 ؋ 8 (256 ؋ 24) Color Palette RAM Three 15 ؋ 8 Overlay Registers On-Board Voltage Reference RS-343A/RS-170 Compatible Analog Outputs TTL Compatible Digital Inputs and Outputs Sync on All Three Channels Programmable Pedestal (0 or 7.5 IRE) Standard MPU l/O Interface +5 V CMOS Monolithic Construction 68-Pin PLCC Package APPLICATIONS High Resolution Color Graphics True-Color Visualization CAE/CAD/CAM Image Processing Desktop Publishing MODES 24-Bit True Color 8-Bit Pseudo Color 15-Bit True Color 8-Bit True Color SPEED GRADES 135 MHz, 110 MHz 80 MHz, 66 MHz GENERAL DESCRIPTION The ADV473 is a complete analog output, Video RAM-DAC on a single CMOS monolithic chip. The part is specifically designed for true-color computer graphics systems. The ADV473 integrates a number of graphic functions onto one device allowing 24-bit direct true-color operation at the maxi- mum screen update rate of 135 MHz. It can also be used in other modes, including 15-bit true color and 8-bit pseudo or in- dexed color. The ADV473 is fully PS/2 and VGA register level compatible. It is also capable of implementing IBM’s XGA standard. (Continued on page 4) FUNCTIONAL BLOCK DIAGRAM VREFIN VREFOUT SYNC BLANK S0 S1 OL0 OVERLAYS OL3 R0 RED R7 G0 GREEN G7 B0 BLUE B7 P I 4X E L P 8 O8 R T 88 88 SWITCHING MATRIX & PIXEL MASK 8 8 8 OVERLAY PALETTE 15 x 8 RAM 15 x 8 RAM 15 x 8 RAM 8 88 RED 256 x 8 RAM COLOR PALETTE GREEN 256 x 8 RAM BLUE 256 x 8 RAM 8 8 8 8 8 8 COLOR PALETTE/ OVERLAY PALETTE SWITCHER 8 8 8 D A C P O R T VOLTAGE REFERENCE GENERATOR VOLTAGE REFERENCE CONTROL CIRCUIT 8 RED DAC 8 GREEN DAC 8 BLUE DAC OPA IOR IOG IOB CLOCK MODE CONTROL PIXEL MASK REGISTERS REGISTERS 8 RED REG 8 GREEN REG 8 BLUE REG MPU PORT 8 ADDRESS REG MPU & PIXEL PORT CONTROL LOGIC ADV473 CR0 CR1 CR2 CR3 D0–D7 RD WR RS0 RS1 RS2 ADV is a registered trademark of Analog Devices Inc. *Personal System/2 and VGA are trademarks of International Business Machines Corp. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 1 page ADV473 PIN FUNCTION DESCRIPTION BLANK SYNC CLOCK R0–R7 B0–B7 G0–G7 S0, S1 OL0–OL3 IOR, IOG, IOB RSET COMP VREFIN VREFOUT VAA GND WR RD RS0, RS1, RS2 D0–D7 CR0–CR7 Composite Blank Control Input (TTL Compatible). A logic zero drives the analog outputs to the blanking level. It is latched on the rising edge of CLOCK. When BLANK is a logical zero, the pixel and overlay inputs are ignored. Composite SYNC Control Input (TTL Compatible). A logical zero on this input switches off a 40 IRE current source on the analog outputs. SYNC does not override any other control or data input; therefore, it should be asserted only during the blanking interval. It is latched on the rising edge of CLOCK. If sync information is not required on the analog outputs, SYNC should be connected to ground. Clock Input (TTL Compatible). The rising edge of CLOCK latches the R0–R7, G0–G7, B0–B7, S0, S1, OL0–OL3, SYNC, and BLANK inputs. It is typically the pixel clock rate of the video system. It is recommended that CLOCK be driven by a dedicated TTL buffer. Red, Green and Blue Select Inputs (TTL Compatible). These inputs specify, on a pixel basis, the color value to be written to the DACs. They are latched on the rising edge of CLOCK. R0, G0 and B0 are the LSBs. Unused inputs should be connected to GND. Color Mode Select Inputs (TTL Compatible). These inputs specify the mode of operation as shown in Table III. They are latched on the rising edge of CLOCK. Overlay Select Inputs (TTL Compatible). These inputs specify which palette is to be used to provide color information. When accessing the overlay palette, the R0–R7, G0–G7, B0–B7, S0 and S1 inputs are ignored. They are latched on the rising edge of CLOCK. OL0 is the LSB. Unused inputs should be connected to GND. Red, Green, and Blue Current Outputs. These high impedance current sources are capable of directly driving a doubly terminated 75 Ω coaxial cable. Full-Scale Adjust Resistor. A resistor (RSET) connected between this pin and GND controls the magnitude of the full-scale video signal. The relationship between RSET and the full-scale output current on each output is: RSET (Ω) = 3,195 × VREF (V)/IOUT (mA) SETUP = 7.5 IRE) RSET (Ω) = 3,025 × VREF (V)/IOUT (mA) SETUP = 0 IRE) Compensation Pin. These pins should be connected together at the chip and connected through 0.1 µF ceramic capacitor to VAA. Voltage Reference Input. This input requires a 1.2 V reference voltage. This is achieved through the on-board voltage reference generator by connecting VREFOUT to VREFIN. If an external reference is used, it must supply this input with a 1.2 V (typical) reference. Voltage Reference Output. This output delivers a 1.2 V reference voltage from the device’s on-board voltage reference generator. It is normally connected directly to the VREFIN pin. If it is preferred to use an external voltage reference, this pin may be left floating. Up to four ADV473s can be driven from VREFOUT. Analog power. All VAA pins must be connected. Analog Ground. All GND pins must be connected. Write Control Input (TTL Compatible). D0–D7 data is latched on the rising edge of WR, and RS0–RS2 are latched on the falling edge of WR during MPU write operations. RD and WR should not be asserted simultaneously. Read Control Input (TTL Compatible). To read data from the device, RD must be a logical zero. RS0–RS2 are latched on the falling edge of RD during MPU read operations. RD and WR should not be asserted simultaneously. Register Select Inputs (TTL Compatible). RS0–RS2 specify the type of read or write operation being performed. Data Bus (TTL Compatible). Data is transferred into and out of the device over this eight-bit bidirectional data bus. D0 is the least significant bit. Control Outputs (TTL Compatible). These outputs are used to control application specific features. The output values are determined by the contents of the command register (CR). REV. A –5– 5 Page ADV473 PC BOARD LAYOUT CONSIDERATIONS The layout should be optimized for lowest noise on the ADV473 power and ground lines by shielding the digital inputs and pro- viding good decoupling. The lead length between groups of VAA and GND pins should be minimized so as to minimize inductive ringing. Ground Planes The ground plane should encompass all ADV473 ground pins, current/voltage reference circuitry, power supply bypass circuitry for the ADV473, the analog output traces, and all the digital sig- nal traces leading up to the ADV473. Power Planes The ADV473 and any associated analog circuitry should have its own power plane, referred to as the analog power plane. This power plane should be connected to the regular PCB power plane (VCC) at a single point through a ferrite bead, as illustrated in Figures 7 and 8. This bead should be located within three inches of the ADV473. The PCB power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all ADV473 power pins and voltage reference circuitry. Plane-to-plane noise coupling can be reduced by ensuring that portions of the regular PCB power and ground planes do not overlay portions of the analog power plane, unless they can be arranged such that the plane-to-plane noise is common mode. Supply Decoupling For optimum performance, bypass capacitors should be installed using the shortest leads possible, consistent with reliable opera- tion, to reduce the lead inductance. Best performance is ob- tained with a 0.1 µF ceramic capacitor decoupling each of the two groups of VAA pins to GND. These capacitors should be placed as close as possible to the device. It is important to note that while the ADV473 contains circuitry to reject power supply noise, this rejection decreases with fre- quency. If a high frequency switching power supply is used, the designer should pay close attention to reducing power supply noise and should consider using a three-terminal voltage regula- tor for supplying power to the analog power plane. Digital Signal Interconnect The digital inputs to the ADV473 should be isolated as much as possible from the analog outputs and other analog circuitry. Also, these input signals should not overlay the analog power plane. Due to the high clock rates involved, long clock lines to the ADV473 should be avoided to reduce noise pickup. Any active termination resistors for the digital inputs should be connected to the regular PCB power plane (VCC), and not to the analog power plane. 0.1µF 0.1µF POWER SUPPLY DECOUPLING (0.1µF CAPACITOR FOR EACH VREF GROUP) +5V (VAA) 0.1µF ANALOG POWER PLANE VAA +5V (VAA) 10µF COMP COMP VREFOUT VREFIN ADV473 +5V (VAA) 1kΩ (1% METAL) AD589 (1.2 VREF ) 0.1µF RSET 140Ω RSET IOR IOG IOB GND 75Ω CO-AXIAL CABLE (75Ω) 75Ω 75Ω 75Ω 75 Ω 75Ω BNC CONNECTORS L1 (FERRITE BEAD) +5V (VCC) 0.1µF MONITOR (CRT) COMPONENT C1 – C5 C6 L1 R1, R2, R3 R4 RSET Z1 DESCRIPTION VENDOR PART NUMBER 0.1µF CERAMIC CAPACITOR 10µF TANTALUM CAPACITOR FERRITE BEAD 75Ω 1% METAL FILM RESISTOR 1kΩ 5% RESISTOR 1% METAL FILM RESISTOR ERIE RPE112Z5U104M50V MALLORY CSR13G106KM FAIR-RITE 2743001111 1.23V VOLTAGE REFERENCE AD589JN Figure 7. Typical Connection Diagram (External Voltage Reference) REV. A –11– 11 Page

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