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PDF ADV453 Data sheet ( Hoja de datos )
| Número de pieza | ADV453 | |
| Descripción | CMOS 66MHz Monolithic 256 x 324 Color Palette RAM-DAC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
CMOS 66 MHz Monolithic 256؋24
Color Palette RAM-DAC
ADV453
FEATURES
66 MHz Pipelined Operation
Triple 8-Bit D/A Converters
256؋24 Color Palette RAM
3؋24 Overlay Registers
RS-343A/RS-170 Compatible Outputs
؉5 V CMOS Monolithic Construction
40-Pin DIP or Small 44-Pin PLCC Package
Power Dissipation: 1000 mW
APPLICATIONS
High Resolution Color Graphics
CAE/CAD/CAM Applications
Image Processing
Instrumentation
Desktop Publishing
AVAILABLE CLOCK RATES
66 MHz
40 MHz
GENERAL DESCRIPTION
The ADV453 is a complete analog video output RAM-DAC on
a single monolithic chip. It is specifically designed for high reso-
lution color graphics systems. The part contains a 256 ϫ 24
color lookup table, a 3 ϫ 24 overlay palette as well as triple 8-bit
video D/A converters. The ADV453 is capable of simulta-
neously displaying up to 259 colors, 256 from the lookup table
and three from the overlay registers, out of a total color palette
of 16.8 million addressable colors.
The three overlay registers allow for implementation of overlay-
ing cursors, pull down menus and grids. There is an indepen-
dent, asynchronous MPU bus which allows access to the color
lookup table without affecting the input of video data via the
pixel port. The ADV453 is capable of generating RGB video
output signals which are compatible with RS-343A and RS-170
video standards, without requiring external buffering.
The ADV453 is fabricated in a +5 V CMOS process. Its mono-
lithic CMOS construction ensures greater functionality with low
power dissipation. The part is packaged in both a 0.6", 40-pin
DIP and a 44-pin plastic leaded (J-lead) chip carrier, PLCC.
FUNCTIONAL BLOCK DIAGRAM
PRODUCT HIGHLIGHTS
1. Fast video refresh rate, 66 MHz.
2. Compatible with a wide variety of high resolution color
graphics systems including VGA* and Macintosh II.**
3. Three overlay registers allow for implementation of overlay-
ing cursors, pull down menus and grids.
4. Guaranteed monotonic. Integral and differential nonlineari-
ties guaranteed to be a maximum of ± 1 LSB.
5. Low glitch energy, 50 pV secs.
**VGA is a trademark of International Business Machines Corp.
**Macintosh II is a registered trademark of Apple Computer Inc.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
ADV453
PIN FUNCTION DESCRIPTION
Pin
Mnemonic
Function
BLANK
SYNC
CLOCK
P0–P7
OL0–OL1
IOR, IOG, IOB
ISYNC
FS ADJUST
COMP
VREF
VAA
GND
CS
WR
RD
C0, C1
D0–D7
Composite blank control input (TTL compatible). A logic zero on this control input drives the analog outputs to
the blanking level, as shown in Table V. The BLANK signal is latched on the rising edge of CLOCK. While
BLANK is at logical zero, the pixel inputs are ignored.
Composite sync control input (TTL compatible). A logical zero on the SYNC input switches off a 40 IRE cur-
rent source on the ISYNC output (see Figure 5). SYNC does not override any other control or data input, as
shown in Table V; therefore, it should only be asserted during the blanking interval. SYNC is latched on the ris-
ing edge of CLOCK.
Clock input (TTL compatible). The rising edge of CLOCK latches the P0–P7 and OL0–OL1 data inputs as well
as the SYNC and BLANK control inputs. It is typically the pixel clock rate of the video system. CLOCK should
be driven by a dedicated TTL buffer.
Pixel select inputs (TTL compatible). These inputs specify, on a pixel basis, which one of the 256 entries in the
color palette RAM is to be used to provide color information. P0–P7 pixel select inputs are latched on the rising
edge of CLOCK. P0 is the LSB. Unused pixel select inputs should be connected to GND.
Overlay select inputs (TTL compatible). These inputs specify which palette is to be used to provide color infor-
mation (see Table IV), i.e., the 256ϫ24 color palette or the 3ϫ24 overlay palette. When accessing the overlay
palette, the P0–P7 inputs are ignored. OL0–OL1 are latched on the rising edge of CLOCK. OL0 is the LSB. Un-
used inputs should be connected to GND.
Red, green and blue current outputs. These high impedance current sources are capable of directly driving a dou-
bly terminated 75 Ω coaxial cable, as shown in Figure 4a. All three current outputs should have similar output
loads whether or not they are all being used.
Sync current output. This high impedance current source can be directly connected to the IOG output (see Fig-
ure 3). This allows sync information to be encoded onto the green channel. ISYNC does not output any current
while SYNC is at logical zero. The amount of current output at ISYNC while SYNC is at logical one is given by:
ISYNC (mA) = 1,728* VREF(V)/RSET(Ω).
If sync information is not required on the green channel, ISYNC should be connected to GND.
Full scale adjust control. A resistor (RSET) connected between this pin and GND (see Figure 6) controls the mag-
nitude of the full scale video signal. Note that the IRE relationships in Figure 5 are maintained, regardless of the
full scale output current.
The relationship between RSET and the full scale output current on IOG (assuming ISYNC is connected to IOG) is
given by:
IOG (mA) = (K + 326 + 1,728)* VREF(V)/RSET(Ω)
The relationship between RSET and the full scale output current on IOR and IOB is given by:
IOR, IOB (mA) = (K + 326)* VREF(V)/RSET(Ω)
where K = 3,993
Compensation pin. This is a compensation pin for the internal reference amplifier. A 0.1 µF ceramic capacitor
must be connected between COMP and VAA (Figure 6).
Voltage reference input. An external 1.235 V voltage reference must be connected to this pin. The use of an ex-
ternal resistor divider network is not recommended. A 0.1 µF decoupling ceramic capacitor should be connected
between VREF and VAA (Figure 6.)
Analog power supply (5 V ± 5%). All VAA pins on the ADV453 must be connected.
Analog ground. All GND pins must be connected.
Chip select control input (TTL compatible). CS must be at logical zero to enable the reading and writing of data
to and from the device. The IOR, IOG and IOB outputs are forced to the black level while CS is at logical zero.
Note that the ADV453 will not operate properly if CS, RD and WR are simultaneously at logical zero.
Write control input (TTL compatible). CS and WR must both be at logical zero when writing data to the device.
D0–D7 data is latched on the rising edge of WR or CS. See Figure 1.
Read control input (TTL compatible). CS and RD must both be at logical zero when reading data from the de-
vice. See Figure 1.
Command control inputs (TTL compatible). C0 and C1 specify the type of read or write operation being carried
out, i.e., address register, color palette RAM or overlay registers read or write operations. See Tables I, II, III.
Data bus (TTL compatible). Data is transferred to and from the address register, the color palette RAM and the
overlay registers over this 8-bit bidirectional data bus. D0 is the least significant bit.
REV. B
–5–
5 Page 
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
40-Pin Plastic DIP
(N-40A)
ADV453
44-Terminal Plastic Leaded Chip Carrier
(P-44A)
REV. B
–11–
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ADV453.PDF ] | |
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