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PDF ADSP-21065LKCA-240 Data sheet ( Hoja de datos )

Número de pieza ADSP-21065LKCA-240
Descripción DSP Microcomputer
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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a
DSP Microcomputer
ADSP-21065L
SUMMARY
High Performance Signal Computer for Communica-
tions, Audio, Automotive, Instrumentation and
Industrial Applications
Super Harvard Architecture Computer (SHARC®)
Four Independent Buses for Dual Data, Instruction,
and I/O Fetch on a Single Cycle
32-Bit Fixed-Point Arithmetic; 32-Bit and 40-Bit Floating-
Point Arithmetic
544 Kbits On-Chip SRAM Memory and Integrated I/O
Peripheral
I2S Support, for Eight Simultaneous Receive and Trans-
mit Channels
KEY FEATURES
66 MIPS, 198 MFLOPS Peak, 132 MFLOPS Sustained
Performance
User-Configurable 544 Kbits On-Chip SRAM Memory
Two External Port, DMA Channels and Eight Serial
Port, DMA Channels
SDRAM Controller for Glueless Interface to Low Cost
External Memory (@ 66 MHz)
64M Words External Address Range
12 Programmable I/O Pins and Two Timers with Event
Capture Options
Code-Compatible with ADSP-2106x Family
208-Lead MQFP or 196-Ball Mini-BGA Package
3.3 Volt Operation
Flexible Data Formats and 40-Bit Extended Precision
32-Bit Single-Precision and 40-Bit Extended-Precision IEEE
Floating-Point Data Formats
32-Bit Fixed-Point Data Format, Integer and Fractional,
with Dual 80-Bit Accumulators
Parallel Computations
Single-Cycle Multiply and ALU Operations in Parallel with
Dual Memory Read/Writes and Instruction Fetch
Multiply with Add and Subtract for Accelerated FFT But-
terfly Computation
1024-Point Complex FFT Benchmark: 0.274 ms (18,221
Cycles)
CORE PROCESSOR
INSTRUCTION
CACHE
32 ؋ 48 BIT
DAG1
DAG2
8 ؋ 4 ؋ 32 8 ؋ 4 ؋ 24
PROGRAM
SEQUENCER
24 PM ADDRESS BUS
32 DM ADDRESS BUS
BUS
CONNECT
(PX)
48 PM DATA BUS
40 DM DATA BUS
DUAL-PORTED SRAM
TWO INDEPENDENT
DUAL-PORTED BLOCKS
PROCESSOR PORT
ADDR
DATA
ADDR
DATA
I/O PORT
DATA
ADDR
ADDR
DATA
IOA IOD
17 48
JTAG
TEST &
EMULATION
7
EXTERNAL
PORT
SDRAM
INTERFACE
ADDR BUS
MUX
24
MULTIPROCESSOR
INTERFACE
DATA BUS
MUX
32
HOST PORT
MULTIPLIER
DATA
REGISTER
FILE
16 ؋ 40 BIT
BARREL
SHIFTER
ALU
IOP
REGISTERS
(MEMORY MAPPED)
CONTROL,
STATUS, TIMER
&
DATA BUFFERS
DMA
CONTROLLER
SPORT 0
SPORT 1
I/O PROCESSOR
Figure 1. Functional Block Diagram
SHARC is a registered trademark of Analog Devices, Inc.
4
(2 Rx, 2Tx)
(I2S)
(2 Rx, 2Tx)
(I2S)
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000

1 page




ADSP-21065LKCA-240 pdf
ADSP-21065L
I/O transfers). Programs can be downloaded to the ADSP-
21065L using DMA transfers. Asynchronous off-chip peripher-
als can control two DMA channels using DMA Request/Grant
lines (DMAR1-2, DMAG1-2). Other DMA features include inter-
rupt generation on completion of DMA transfers and DMA
chaining for automatically linked DMA transfers.
Serial Ports
The ADSP-21065L features two synchronous serial ports that
provide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices. The serial ports can operate at
1x clock frequency, providing each with a maximum data rate of
33 Mbit/s. Each serial port has a primary and a secondary set of
transmit and receive channels. Independent transmit and receive
functions provide greater flexibility for serial communications.
Serial port data can be automatically transferred to and from
on-chip memory via DMA. Each of the serial ports supports
three operation modes: DSP serial port mode, I2S mode (an
interface commonly used by audio codecs), and TDM (Time
Division Multiplex) multichannel mode.
The serial ports can operate with little-endian or big-endian
transmission formats, with selectable word lengths of 3 bits to
32 bits. They offer selectable synchronization and transmit
modes and optional µ-law or A-law companding. Serial port
clocks and frame syncs can be internally or externally generated.
The serial ports also include keyword and keymask features to
enhance interprocessor communication.
Programmable Timers and General Purpose I/O Ports
The ADSP-21065L has two independent timer blocks, each of
which performs two functions—Pulsewidth Generation and
Pulse Count and Capture.
In Pulsewidth Generation mode, the ADSP-21065L can gener-
ate a modulated waveform with an arbitrary pulsewidth within
a maximum period of 71.5 secs.
In Pulse Counter mode, the ADSP-21065L can measure either
the high or low pulsewidth and the period of an input waveform.
The ADSP-21065L also contains twelve programmable, general
purpose I/O pins that can function as either input or output. As
output, these pins can signal peripheral devices; as input, these
pins can provide the test for conditional branching.
Program Booting
The internal memory of the ADSP-21065L can be booted at
system power-up from an 8-bit EPROM, a host processor, or
external memory. Selection of the boot source is controlled by
the BMS (Boot Memory Select) and BSEL (EPROM Boot)
pins. Either 8-, 16-, or 32-bit host processors can be used for
booting. For details, see the descriptions of the BMS and BSEL
pins in the Pin Descriptions section of this data sheet.
Multiprocessing
The ADSP-21065L offers powerful features tailored to multi-
processing DSP systems. The unified address space allows
direct interprocessor accesses of both ADSP-21065L’s IOP
registers. Distributed bus arbitration logic is included on-chip
for simple, glueless connection of systems containing a maxi-
mum of two ADSP-21065Ls and a host processor. Master pro-
cessor changeover incurs only one cycle of overhead. Bus lock
allows indivisible read-modify-write sequences for semaphores.
A vector interrupt is provided for interprocessor commands.
Maximum throughput for interprocessor data transfer is
132 Mbytes/sec over the external port.
DEVELOPMENT TOOLS
The ADSP-21065L is supported with a complete set of software
and hardware development tools, including the EZ-ICE® In-
Circuit Emulator and development software.
The same EZ-ICE hardware that you use for the ADSP-21060/
ADSP-21062 also fully emulates the ADSP-21065L.
Both the SHARC Development Tools family and the VisualDSP®
integrated project management and debugging environment
support the ADSP-21065L. The VisualDSP project manage-
ment environment enables you to develop and debug an appli-
cation from within a single integrated program.
The SHARC Development Tools include an easy to use Assem-
bler that is based on an algebraic syntax; an Assembly library/
librarian; a linker; a loader; a cycle-accurate, instruction-level
simulator; a C compiler; and a C run-time library that includes
DSP and mathematical functions.
Debugging both C and Assembly programs with the Visual DSP
debugger, you can:
• View Mixed C and Assembly Code
• Insert Break Points
• Set Watch Points
• Trace Bus Activity
• Profile Program Execution
• Fill and Dump Memory
• Create Custom Debugger Windows
The Visual IDE enables you to define and manage multiuser
projects. Its dialog boxes and property pages enable you to
configure and manage all of the SHARC Development Tools.
This capability enables you to:
• Control how the development tools process inputs and gen-
erate outputs.
• Maintain a one-to-one correspondence with the tool’s com-
mand line switches.
The EZ-ICE Emulator uses the IEEE 1149.1 JTAG test access
port of the ADSP-21065L processor to monitor and control the
target board processor during emulation. The EZ-ICE provides
full-speed emulation, allowing inspection and modification of
memory, registers, and processor stacks. Nonintrusive in-circuit
emulation is assured by the use of the processor’s JTAG inter-
face—the emulator does not affect target system loading or
timing.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the SHARC processor family. Hard-
ware tools include SHARC PC plug-in cards multiprocessor
SHARC VME boards, and daughter and modules with multiple
SHARCs and additional memory. These modules are based on
the SHARCPAC™ module specification. Third Party software
tools include an Ada compiler, DSP libraries, operating systems,
and block diagram design tools.
Additional Information
For detailed information on the ADSP-21065L instruction set
and architecture, see the ADSP-21065L SHARC User’s Manual,
Third Edition, and the ADSP-21065L SHARC Technical Reference.
EZ-ICE and VisualDSP are registered trademarks of Analog Devices, Inc.
SHARCPAC is a trademark of Analog Devices Inc.
REV. B
–5–

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ADSP-21065LKCA-240 arduino
The BTMS, BTCK, BTRST and BTDI signals are provided so
that the test access port can also be used for board-level testing.
When the connector is not being used for emulation, place
jumpers between the Bxxx pins and the xxx pins. If you are not
going to use the test access port for board testing, tie BTRST
to GND and tie or pull-up BTCK to VDD. The TRST pin must
be asserted after power-up (through BTRST on the connector)
or held low for proper operation of the ADSP-2106x. None of
the Bxxx pins (Pins 5, 7, 9, 11) are connected on the EZ-ICE
probe.
The JTAG signals are terminated on the EZ-ICE probe as follows:
Signal
Termination
TMS
TCK
TRST*
TDI
TDO
CLKIN
EMU
Driven through 22 resistor (16 mA driver)
Driven at 10 MHz through 22 resistor
(16 mA driver)
Driven through 22 resistor (16 mA driver)
(pulled up by on-chip 20 kresistor)
Driven by 22 resistor (16 mA driver)
One TTL load, Split Termination (160/220)
One TTL load, Split Termination (160/220).
(Caution: Do not connect to CLKIN if
internal XTAL oscillator is used.)
Active Low 4.7 kpull-up resistor, one TTL
load (open-drain output from ADSP-2106xs)
*TRST is driven low until the EZ-ICE probe is turned on by the emulator at
software start-up. After software start-up, TRST is driven high.
ADSP-21065L
Connecting CLKIN to Pin 4 of the EZ-ICE header is optional.
The emulator only uses CLKIN when directed to perform op-
erations such as starting, stopping, and single-stepping two
ADSP-21065Ls in a synchronous manner. If you do not need
these operations to occur synchronously on the two processors,
simply tie Pin 4 of the EZ-ICE header to ground.
For systems which use the internal clock generator and an exter-
nal discrete crystal, do not directly connect the CLKIN pin to
the JTAG probe. This will load the oscillator circuit and possi-
bly cause it to fail to oscillate. Instead the JTAG probe’s
CLKIN can be driven by the XTAL pin through a high imped-
ance buffer.
If synchronous multiprocessor operations are needed and CLKIN
is connected, clock skew between multiple ADSP-2106x proces-
sors and the CLKIN pin on the EZ-ICE header must be mini-
mal. If the skew is too large, synchronous operations may be off
by one cycle between processors. For synchronous multiproces-
sor operation TCK, TMS, CLKIN and EMU should be treated
as critical signals in terms of skew, and should be laid out as
short as possible on your board.
If synchronous multiprocessor operations are not needed (i.e.,
CLKIN is not connected), just use appropriate parallel termina-
tion on TCK and TMS. TDI, TDO, EMU and TRST are not
critical signals in terms of skew.
For Complete information on the SHARC EZ-ICE, see the
ADSP-21000 Family JTAG EZ-ICE User’s Guide and Reference.
REV. B
–11–

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