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PDF AK2306LV Data sheet ( Hoja de datos )
| Número de pieza | AK2306LV | |
| Descripción | Dual PCM CODEC for ISDN/VoIP TERMINAL ADAPTER | |
| Fabricantes | Asahi Kasei Microsystems | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AK2306LV (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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ASAHI KASEI
[AK2306/LV]
AK2306/2306LV
Dual PCM CODEC for ISDN/VoIP TERMINAL ADAPTER
GENERAL DESCRIPTION
AK2306 is a dual PCM CODEC-Filter most suitable for
ISDN Terminal Adapter.
It includes Selectable A-law/u-law function, Internal
Gain Adjustment from +6dB to –18dB by 1dB step
control, Selectable 16Hz/20Hz Ring Tone Generator for
SLIC. All of these functions are controlled by the
internal register accessed through the serial interface.
PCM interface of AK2306 accepts Long Frame, Short
Frame clock formats and GCI format. 64 x N
kHz(128k-4096kHz) clock input is available for PCM
interface.
AK2306 and AK2306LV are pin-compatible, but
different products which power supply voltage are 5.0V
and 3.3V,respectively.
FEATURE
- Dual PCM CODEC and Filtering systems for
ISDN Terminal Adapter
- Selectable Ring Tone Generator for SLIC
16Hz or 20Hz tone is available.
- Independent functions on each channel
controlled by the internal register
- Power Down Mode
- Mute
- Gain Adjustment: +6 to -18dB (1dB step)
- Selectable PCM Data Interface Timing:
Long Frame / Short Frame/GCI
- Variable PCM Data Rate:
64k x N [Hz] (128k - 4.096MHz)
- OP Amp for External Gain Adjustment
- A-law/u-law Register Selectable
- Serial Interface to access the internal register
- Power on Reset
- Single Power Supply Voltage
- +5.0V ± 5% (AK2306)
- +3.3V ± 0.3V (AK2306LV)
- Low Power Consumption
PACKAGE
- 24pinVSOP
7.9 x 7.6 mm (0.5mm pin pitch)
MS0093-E-04 1 2001/11
1 page  
ASAHI KASEI
PIN CONDITION
[AK2306/LV]
Pin# Name I/O
Pin type
AC load
(MAX.)
DC load
(MIN.)
Outout status
(Power down
mode)
Output status
(Reset)
Remarks
VFTP1
Analog
VFTN1
Analog
GST1
Analog
50pF
10kΩ(*1)
Hi-Z
Hi-Z
GSR1
O
Analog
50pF
10kΩ (*1)
Hi-Z
Hi-Z
VFR1
I
Analog
VR1 O Analog
50pF
10kΩ
Hi-Z
Hi-Z
VDD
-
FS I TTL/CMOS(*3)
BCLK
I TTL/CMOS(*3)
DX O CMOS
15pF
Hi-Z Hi-Z
DR I TTL/CMOS(*3)
TNOUT O
CMOS
15pF
LL
SCLK
I TTL/CMOS(*3)
DATA
I/O TTL/CMOS(*3)
15pF
Input
Input
CSN
I TTL/CMOS(*3)
LPC O Analog
0.22uF (*2)
VSS
-
VR0 O Analog
50pF
10kΩ
Hi-Z
Hi-Z
VFR0
I
Analog
GSR0
O
Analog
50pF
10kΩ (*1)
Hi-Z
Hi-Z
GST0
I
Analog
50pF
10kΩ (*1)
Hi-Z
Hi-Z
VFTN0
O
Analog
VFTP0
O
Analog
VREF
O
Analog
1.0 uF (*2)
*1) DC load(MIN.) includes a feedback resistance of input/output op-amp.
*2)External capacitance should be connected to VSS.
*3)TTL level is applied only for the input level of AK2306LV. Output level for both AK2306 and AK230LV,and
the input level of AK2306 are CMOS level.
MS0093-E-04 5 2001/11
5 Page 
ASAHI KASEI
[AK2306/LV]
GCI ( General Circuit Interface )
GCI format is used for ISDN application. The data format and clocking is showed as Fig X.
timing of the interface
8 bits PCM data is accommodated in 1 frame( 125us ) defined by 8kHz frame sync signal.
Although there are 32 time slots at maximum in 8kHz frame(when BCK=4.096MHz), PCM data on GCI occupy
first and second time slot for channel 0 and channel 1,respectively.
Frame Sync signal (FS)
8kHz reference signal. This signal indicated the timing and the frame position of 8kHz GCI. All the internal clock
of the LSI is generated based on this FS signal. High level duration of the FS is 1 clock period of BCLK.
Bit Clock (BCLK)
BCLK defines the GCI data rate. The bit rate of GCI data is half of BCLK. BCLK can be varied from 512kHz to 4.096MHz by
128kHz step.
Position of the Ch0,Ch1 GCI data in the DX/DR data flow
B1 and B2 channel of the GCI data channel are assigned to Analog Ch0 and Ch1 as is defined by SEL2B register
as same way as PCM interface.
CH0,1selection( Address:100 Bit:5)
SEL2B
CH0
0 B1
CH1
B2
1 B2 B1
Remarks
Default
on Reset
<2ch Multiplex>
FS
BCLK
DX
B1 ch
B2 ch
1234567812345678
DR
Don’t
care
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Don’t
care
SEL2B=0 =>
SEL2B=1 =>
B1-CHANNEL (CH0)
B1-CHANNEL (CH1)
B2-CHANNEL (CH1)
B2-CHANNEL (CH0)
<Non Multiplex>
Not supported
! Important Notice
Please don’t stop feeding FS and BCLK except Full power down mode.
Internal PLL does free running when either FS or BCLK is not provided. In this case, the frequency of Ring Tone output
is not guaranteed.
MS0093-E-04 11 2001/11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AK2306LV.PDF ] | |
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