PDF ADV7300A Data sheet ( Hoja de datos )

Número de pieza	ADV7300A
Descripción	Multiformat SD/ Progressive Scan/HDTV Video Encoder with Six NSV 12-Bit DACs
Fabricantes	Analog Devices
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No Preview Available ! a Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV™ 12-Bit DACs ADV7300A/ADV7301A FEATURES High Definition Input Formats YCrCb Compliant to SMPTE293M (525 p), ITU-R.BT1358 (625 p), SMPTE274M (1080 i), SMPTE296M (720 p), and Any Other High Definition Standard Using Async Timing Mode RGB in 3 ؋ 10-Bit 4:4:4 Format BTA T-1004 EDTV2 525 p Parallel High Definition Output Formats (525 p/625 p/720 p/1080 i) YPrPb Progressive Scan (EIA-770.1, EIA-770.2) YPrPb HDTV (EIA 770.3) RGB + H/V (HDTV 5-Wire Format) CGMS-A (720 p/1080 i) Macrovision Rev 1.0 (525 p/625 p)* CGMS-A (525 p) Standard Definition Input Formats CCIR-656 4:2:2 8-/10-Bit Parallel Input CCIR-601 4:2:2 16-/20-Bit Parallel Input Standard Definition Output Formats Composite NTSC M, N; PAL M, N, B, D, G, H, I, PAL-60 SMPTE170M NTSC Compatible Composite Video ITU-R.BT470 PAL Compatible Composite Video S-Video (Y/C) EuroScart RGB Component YUV (Betacam, MII, SMPTE/EBU N10) Macrovision Rev 7.1* CGMS/WSS Closed Captioning GENERAL FEATURES Simultaneous SD and HD Inputs and Outputs Oversampling (108 MHz/148.5 MHz) On-Board Voltage Reference 6 NSV Precision Video 12-Bit DACs 2-Wire Serial MPU Interface Dual I/O Supply 2.5 V/3.3 V Operation Analog and Digital Supply 2.5 V On-Board PLL 64-LQFP Package Lead-Free Product APPLICATIONS High End DVD Players SD/Program Scan/HDTV Display Devices SD/Program Scan/HDTV Set-Top Boxes SD/HDTV Studio Equipment SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM S9–S0 Y9–Y0 C9–C0 S_HSYNC S_VSYNC S_BLANK P_HSYNC P_VSYNC P_BLANK CLKIN_A CLKIN_B STANDARD DEFINITION CONTROL BLOCK COLOR CONTROL D BRIGHTNESS E DNR M GAMMA U PROGRAMMABLE FILTERS X SD TEST PATTERN PROGRAMMABLE RGB MATRIX D E M U X TIMING GENERATOR HIGH DEFINITION CONTROL BLOCK HD TEST PATTERN COLOR CONTROL ADAPTIVE FILTER CTRL SHARPNESS FILTER PLL ADV7300A/ ADV7301A 12-BIT DAC O 12-BIT V DAC E R S A 12-BIT DAC M P 12-BIT L DAC I N 12-BIT G DAC 12-BIT DAC I2C INTERFACE GENERAL DESCRIPTION The ADV7300A/ADV7301A is a high speed, digital-to-analog encoder on a single monolithic chip. It includes six high speed video D/A converters with TTL compatible inputs. The ADV7300A/ADV7301A has three separate 10-bit wide input ports that accept data in high definition and/or standard defini- tion video format. For all standards, external horizontal, vertical, and blanking signals, or EAV/SAV timing codes, control the insertion of appropriate synchronization signals into the digital data stream and therefore the output signals. NSV (Noise Shaped Video) is a trademark of Analog Devices, Inc. *ADV7300A Only REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 1 page ADV7300A/ADV7301A TIMING SPECIFICATIONS (VAA = VDD = 2.375 V–2.625 V, VDD_IO = 2.375 V–3.600 V, VREF = 1.235 V, RSET = 760 ⍀, RLOAD = 150 ⍀, TMIN to TMAX (0؇C to 70؇C), unless otherwise noted.) Parameter Min Typ Max Unit Test Conditions MPU PORT1 SCLOCK Frequency SCLOCK High Pulsewidth, t1 SCLOCK Low Pulsewidth, t2 Hold Time (Start Condition), t3 Setup Time (Start Condition), t4 Data Setup Time, t5 SDATA, SCLOCK Rise Time, t6 SDATA, SCLOCK Fall Time, t7 Setup Time (Stop Condition), t8 RESET Low Time 0 0.6 1.3 0.6 0.6 100 0.6 100 400 kHz µs µs µs µs ns 300 ns 300 ns µs ns First Clock Generated after This Period Relevant for Repeated Start Condition ANALOG OUTPUTS Analog Output Delay2 Output Skew 8 ns 1 ns CLOCK CONTROL AND PIXEL PORT3 fCLK fCLK Clock High Time, t9 Clock Low Time, t10 Data Setup Time, t11 Data Hold Time, t12 Output Access Time, t13 Output Hold Time, t14 Pipeline Delay 40 40 2.0 2.0 4.0 27 81 14 61 62.5 66.5 33 43.5 36 MHz MHz % 1 clkcycle % 1 clkcycle ns ns ns ns clkcycles clkcycles clkcycles clkcycles clkcycles clkcycles Progressive Scan Mode HDTV Mode/Async Mode SD [2ϫ] SD [8ϫ] SD Component Filter [8ϫ] PS [1ϫ], HD [1ϫ], Async Timing Mode PS [4ϫ] HD [2ϫ] NOTES 1Guaranteed by characterization. 2Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition. 3Data: C[9:0]; S[9:0]; Y[9:0] Control: P_HSYNC; P_ VSYNC; P_BLANK; S_HSYNC; S_VSYNC; S_BLANK Specifications subject to change without notice. REV. A –5– 5 Page ADV7300A/ADV7301A P_HSYNC P_VSYNC P_BLANK Y9–Y0 a Y0 Y1 Y2 Y3 S9–S0 C9–C0 b a = 16 CLKCYCLES FOR 525p a = 12 CLKCYCLES FOR 626p a = 44 CLKCYCLES FOR 1080i a = 70 CLKCYCLES FOR 720p AS RECOMMENDED BY STANDARD b(MIN) = 122 CLKCYCLES FOR 525p b(MIN) = 132 CLKCYCLES FOR 625p b(MIN) = 236 CLKCYCLES FOR 1080i b(MIN) = 300 CLKCYCLES FOR 720p Figure 12. HD Input Timing Diagram HSYNC Cr0 Cr1 Cr2 Cr3 Cb0 Cb1 Cb2 Cb3 FIELD BLANK PIXEL DATA SDA SCLK PAL = 12 ؋ CLOCK/2 NTSC = 16 ؋ CLOCK/2 Cb Y Cr Y PAL = 132 ؋ CLOCK/2 NTSC = 122 ؋ CLOCK/2 Figure 13. SD Timing Input for Timing Mode 1 t3 t5 t3 t6 t1 t2 t7 t4 Figure 14. MPU Port Timing Diagram t8 REV. A –11– 11 Page

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