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PDF AT89C5131 Datasheet ( Hoja de datos )

Número de pieza AT89C5131
Descripción 8-bit Flash Microcontroller
Fabricantes ATMEL Corporation 
Logotipo ATMEL Corporation Logotipo
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AT89C5131 datasheet

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AT89C5131 pdf
Figure 2. AT89C5131 64-pin VQFP Pinout
AT89C5131
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
NC 1
P2.3/A11 2
P2.4/A12 3
P2.5/A13 4
XTAL2
XTAL1
P2.6/A14
5
6
7
P2.7/A15 8
VDD 9
AVDD 10
NC 11
AVSS 12
NC 13
P3.0/RxD 14
NC 15
NC 16
VQFP64
48 NC
47 NC
46 P0.1/AD1
45 P0.2/AD2
44 RST
43 P0.3/AD3
42 VSS
41 NC
40 P0.4/AD4
39 P3.7/RD/LED3
38 P0.5/AD5
37 P0.6/AD6
36 P0.7/AD7
35 P3.6/WR/LED2
34 NC
33 NC
17 18 19 20 21 22 23 24 25 26 27 28 29 30 3132
4136C–USB–04/05
5

5 Page

AT89C5131 arduino
Table 11. System Signal Description
Signal
Name Type Description
Alternate
Function
AD[7:0]
Multiplexed Address/Data LSB for external access
I/O
Data LSB for Slave port access (used for 8-bit and 16-bit modes)
P0[7:0]
A[15:8]
Address Bus MSB for external access
I/O
Data MSB for Slave port access (used for 16-bit mode only)
P2[7:0]
Read Signal
RD I/O Read signal asserted during external data memory read operation.
Control input for slave port read access cycles.
P3.7
Write Signal
WR I/O Write signal asserted during external data memory write operation.
Control input for slave write access cycles.
P3.6
RST
Reset Input
Holding this pin low for 64 oscillator periods while the oscillator is running
resets the device. The Port pins are driven to their reset conditions when a
voltage lower than VIL is applied, whether or not the oscillator is running.
I
This pin has an internal pull-up resistor which allows the device to be reset
by connecting a capacitor between this pin and VSS.
Asserting RST when the chip is in Idle mode or Power-down mode returns
the chip to normal operation.
This pin is set to 0 for at least 12 oscillator periods when an internal reset
occurs.
-
Address Latch Enable Output
ALE
O
The falling edge of ALE strobes the address into external latch. This signal
is active only when reading or writing external memory using MOVX
instructions.
-
PSEN
EA
O
Program
Test mode entry signal. This pin must be set to VDD for normal operation.
External Access Enable
I This pin must be held low to force the device to fetch code from external
program memory starting at address 0000h. It is latched during reset and
cannot be dynamically changed during operation.
-
-
Table 12. Power Signal Description
Signal
Name Type Description
AVSS
GND
Alternate Ground
AVSS is used to supply the on-chip PLL and the USB PAD.
AVDD
PWR
Alternate Supply Voltage
AVDD is used to supply the on-chip PLL and the USB PAD.
VSS
GND
Digital Ground
VSS is used to supply the buffer ring and the digital core.
VDD
PWR
Digital Supply Voltage
VDD is used to supply the buffer ring on all versions of the device.
It is also used to power the on-chip voltage regulator of the Standard
versions or the digital core of the Low Power versions.
Alternate
Function
-
-
-
-
10 AT89C5131
4136C–USB–04/05

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