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PDF BDGLA16E-TR Datasheet ( Hoja de datos )

Número de pieza BDGLA16E-TR
Descripción Quad Differential Drivers BDG1A/ BDP1A/ BDGLA/ BPNGA/ BPNPA/ and BPPGA
Fabricantes Agere Systems 
Logotipo Agere Systems Logotipo

Total 16 Páginas
		
BDGLA16E-TR Hoja de datos, Descripción, Manual
Data Sheet
January 1999
Quad Differential Drivers
BDG1A, BDP1A, BDGLA, BPNGA, BPNPA, and BPPGA
Features
s Pin-equivalent to the general-trade 26LS31 device,
with improved speed, reduced power consumption,
and significantly lower levels of EMI
s Four line drivers per package
s Meets ESDI standards
s 2.0 ns maximum propagation delay
s Single 5.0 V ± 10% supply
s Operating temperature range: 40 °C to +125 °C
(wider than the 41 Series)
s 400 Mbits/s maximum data rate
s Logic to convert TTL input logic levels to differen-
tial, pseudo-ECL output logic levels
s No line loading when VCC = 0 (BDG1A, BDP1A
only)
s High output driver for 50 loads
s <0.2 ns output skew (typical)
s On-chip 220 loads available
s Third-state outputs available
s Surge-protection to ±60 V for 10 ms available
(BPNGA, BPNPA, BPPGA)
s Available in four package types
s ESD performance better than the 41 Series
s Lower power requirement than the 41 Series
Description
These quad differential drivers are TTL input-to-
pseudo-ECL-differential-output used for digital data
transmission over balanced transmission lines. All
devices in this family have four drivers with a single
enable control in a common package. These drivers
are compatible with many receivers, including the
Lucent Technologies Microelectronics Group 41
Series receivers and transceivers. They are pin
equivalent to the general-trade 26LS31, but offer
increased speed, decreased power consumption,
and significantly lower levels of electromagnetic inter-
ference (EMI). They replace the Lucent 41 Series
drivers.
The BDG1A device is the generic driver in this family
and requires the user to supply external resistors on
the circuit board for impedance matching.
The BDGLA is a low-power version of the BDG1A,
reducing the power requirement by more than one
half. The BDGLA features a 3-state output with a typ-
ical third-state level of 0.2 V.
The BDP1A is equivalent to the BDG1A but has
220 termination resistors to ground on each driver
output. This eliminates the need for external pull-
down resistors when driving a 100 impedance line.
The BPNGA and BPNPA are equivalent to the
BDG1A and BDP1A, respectively, except that a light-
ning protection circuit has been added to the driver
outputs. This circuit will absorb large transitions on
the transmission lines without destroying the device.
The BPPGA combines the features of the BPNGA
and BPNPA. Two of the gates have their outputs ter-
minated to ground through 220 resistors while the
two remaining gates require external termination
resistors.
When the BDG1A and the BDP1A devices are pow-
ered down, the output circuit appears as an open cir-
cuit relative to the power supplies; hence, they will
not load the transmission line. For those circuits with
termination resistors, the line will remain impedance
matched when the circuit is powered down. The
BPNGA, BPNPA, BPPGA, and BDGLA will load the
transmission line, because of the protection circuit,
when the circuit is powered down.
The packaging options that are available for these
quad differential line drivers include a 16-pin DIP; a
16-pin, J-lead SOJ; a 16-pin, gull-wing SOIC; and a
16-pin, narrow-body, gull-wing SOIC.

1 page

BDGLA16E-TR pdf
Data Sheet
January 1999
Quad Differential Drivers
BDG1A, BDP1A, BDGLA, BPNGA, BPNPA, and BPPGA
Timing Characteristics
Table 4. Timing Characteristics (See Figures 2 and 3.)
For tP1 and tP2 propagation delays over the temperature range, see Figure 9.
Propagation delay test circuit connected to output (see Figure 6).
TA = –40 °C to +125 °C, VCC = 5 V ± 0.5 V.
Parameter
Symbol
Min
Typ
Max
Propagation Delay:
Input High to Output
Input Low to Output
Capacitive Delay
Disable Time (either E1 or E2):
High-to-high Impedance
Low-to-high Impedance
Enable Time (either E1 or E2):
High Impedance to High
High Impedance to Low
Output Skew, |tP1 – tP2|
|tPHH – tPHL|, |tPLH – tPLL|
Difference Between Drivers
Rise Time (20%—80%)
Fall Time (80%—20%)
tP1*
tP2*
tp
tPHZ
tPLZ
tPZH
tPZL
tskew1
tskew2
tskew
ttLH
ttHL
0.8
0.8
4
4
4
4
1.2
1.2
0.02
8
8
8
8
0.1
0.2
0.7
0.7
2.0
2.0
0.03
12
12
12
12
0.3
0.5
0.3
2
2
* tP1 and tP2 are measured from the 1.5 V point of the input to the crossover point of the outputs (see Figure 2).
† CL = 5 pF. Capacitor is connected from each output to ground.
Unit
ns
ns
ns/pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
Lucent Technologies Inc.
5

5 Page

BDGLA16E-TR arduino
Data Sheet
January 1999
Outline Diagrams (continued)
16-Pin SOIC (SONB/SOG)
Dimensions are in millimeters.
Quad Differential Drivers
BDG1A, BDP1A, BDGLA, BPNGA, BPNPA, and BPPGA
L
N
B
1
PIN #1 IDENTIFIER ZONE
W
1.27 TYP
0.51 MAX
H
SEATING PLANE
0.10
0.28 MAX
0.61
5-4414r.3 (C)
Package
Description
SONB (Small-
Outline, Narrow
Body)
SOG (Small-
Outline, Gull-
Wing)
Number of
Pins
(N)
16
16
Maximum Length
(L)
10.11
10.49
Package Dimensions
Maximum Width Maximum Width
Without Leads Including Leads
(B) (W)
4.01 6.17
7.62 10.64
Maximum Height
Above Board
(H)
1.73
2.67
Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schematics to assist your design efforts,
please contact your Lucent Technologies Sales Representative.
Lucent Technologies Inc.
11

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