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PDF M28F201 Data sheet ( Hoja de datos )

Número de pieza M28F201
Descripción 2 Mb FLASH MEMORY
Fabricantes STMicroelectronics 
Logotipo STMicroelectronics Logotipo



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No Preview Available ! M28F201 Hoja de datos, Descripción, Manual

M28F201
2 Mb (256K x 8, Chip Erase) FLASH MEMORY
5V ± 10% SUPPLY VOLTAGE
12V PROGRAMMING VOLTAGE
FAST ACCESS TIME: 70ns
BYTE PROGRAMMING TIME: 10µs typical
ELECTRICAL CHIP ERASE in 1s RANGE
LOW POWER CONSUMPTION
– Active Current: 15mA typical
– Stand-by Current: 10µA typical
10,000 PROGRAM/ERASE CYCLES
INTEGRATED ERASE/PROGRAM-STOP
TIMER
OTP COMPATIBLE PACKAGES and PINOUTS
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: F4h
PLCC32 (K)
Figure 1. Logic Diagram
TSOP32 (N)
8 x 20 mm
DESCRIPTION
The M28F201 FLASH Memory product is a non-
volatile memories which may be erased electrically
at the chip level and programmed byte-by-byte. It
is organised as 256K bytes. It uses a command
register architecture to select the operating modes
and thus provide a simple microprocessor inter-
face. The M28F201 FLASH Memory product is
suitable for applications where the memory has to
be reprogrammed in the equipment. The access
time of 70ns makes the device suitable for use in
high speed microprocessor systems.
Table 1. Signal Names
A0-A17
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
E Chip Enable
G Output Enable
W Write Enable
VPP Program Supply
VCC Supply Voltage
VSS Ground
VCC VPP
18
A0-A17
8
DQ0-DQ7
W M28F201
E
G
VSS
AI00637C
April 1997
1/21

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M28F201 pdf
Table 6. AC Measurement Conditions
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
SRAM Interface Levels
10ns
0 to 3V
1.5V
M28F201
EPROM Interface Levels
10ns
0.45V to 2.4V
0.8V and 2V
Figure 3. AC Testing Input Output Waveform
SRAM Interface
3V
0V
EPROM Interface
2.4V
0.45V
1.5V
2.0V
0.8V
AI01275
Figure 4. AC Testing Load Circuit
1.3V
1N914
DEVICE
UNDER
TEST
3.3k
OUT
CL = 30pF or 100pF
CL = 30pF for SRAM Interface
CL = 100pF for EPROM Interface
CL includes JIG capacitance
AI01276
Table 7. Capacitance (1) (TA = 25 °C, f = 1 MHz )
Symbol
Parameter
Test Condition
CIN Input Capacitance
VIN = 0V
COUT
Output Capacitance
Note: 1. Sampled only, not 100% tested.
VOUT = 0V
Min Max Unit
6 pF
12 pF
Read Mode. The Read Mode is the default at
power up or may be set-up by writing 00h to the
command register. Subsequent read operations
output data from the memory. The memory remains
in the Read Mode until a new command is written
to the command register.
Electronic Signature Mode. In order to select the
correct erase and programming algorithms for on-
board programming, the manufacturer and device
codes may be read directly. It is not neccessary to
apply a high voltage to A9 when using the com-
mand register. The Electronic Signature Mode is
set-up by writing 80h or 90h to the command
register. The following read cycles, with address
inputs 00000h or 00001h, output the manufacturer
or device codes. The command is terminated by
writing another valid command to the command
register (for example Reset).
5/21

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M28F201 arduino
M28F201
Table 10B. Read/Write Mode AC Characteristics, W and E Controlled
(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)
M28F201
Symbol Alt
Parameter
-120
VCC = 5V ± 10%
EPROM
Interface
-150
VCC = 5V ± 10%
EPROM
Interface
Unit
Min Max Min Max
tVPHEL
VPP High to Chip Enable Low
1 1 µs
tVPHWL
VPP High to Write Enable Low
1 1 µs
tWHWH3 tWC Write Cycle Time (W controlled)
120 150 ns
tEHEH3 tWC Write Cycle Time (E controlled)
120 150 ns
tAVWL
tAS Address Valid to Write Enable Low
0 0 ns
tAVEL
Address Valid to Chip Enable Low
0 0 ns
tWLAX
tAH Write Enable Low to Address Transition
50 50 ns
tELAX
Chip Enable Low to Address Transition
60 80 ns
tELWL
tCS Chip Enable Low to Write Enable Low
0 0 ns
tWLEL
Write Enable Low to Chip Enable Low
0 0 ns
tGHWL
Output Enable High to Write Enable Low
0 0 µs
tGHEL
Output Enable High to Chip Enable Low
0 0 µs
tDVWH
tDS Input Valid to Write Enable High
50 50 ns
tDVEH
Input Valid to Chip Enable High
50 50 ns
tWLWH tWP Write Enable Low to Write Enable High (Write Pulse)
50
60 ns
tELEH
Chip Enable Low to Chip Enable High (Write Pulse)
70
80 ns
tWHDX
tDH Write Enable High to Input Transition
10 10 ns
tEHDX
Chip Enable High to Input Transition
10 10 ns
tWHWH1
Duration of Program Operation (W contr.)
10 10 µs
tEHEH1
Duration of Program Operation (E contr.)
10 10 µs
tWHWH2
Duration of Erase Operation (W contr.)
9.5 9.5 ms
tEHEH2
Duration of Erase Operation (E contr.)
9.5 9.5 ms
tWHEH
tCH Write Enable High to Chip Enable High
0 0 ns
tEHWH
Chip Enable High to Write Enable High
0 0 ns
tWHWL tWPH Write Enable High to Write Enable Low
20 20 ns
tEHEL
Chip Enable High to Chip Enable Low
20 20 ns
tWHGL
Write Enable High to Output Enable Low
6 6 µs
tEHGL
Chip Enable High to Output Enable Low
6 6 µs
tAVQV
tELQX (1)
tACC Addess Valid to data Output
tLZ Chip Enable Low to Output Transition
120 150 ns
0 0 ns
tELQV
tGLQX (1)
tCE Chip Enable Low to Output Valid
tOLZ Output Enable Low to Output Transition
120 150 ns
0 0 ns
tGLQV
tEHQZ (1)
tGHQZ (1)
tOE Output Enable Low to Output Valid
Chip Enable High to Output Hi-Z
tDF Output Enable High to Output Hi-Z
35 40 ns
30 35 ns
30 35 ns
tAXQX
tOH Address Transition to Output Transition
0 0 ns
Note: 1. Sampled only, not 100% tested
11/21

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