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PDF M28C16 Data sheet ( Hoja de datos )

Número de pieza M28C16
Descripción 16K (2K x 8) PARALLEL EEPROM
Fabricantes STMicroelectronics 
Logotipo STMicroelectronics Logotipo



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No Preview Available ! M28C16 Hoja de datos, Descripción, Manual

M28C16
16K (2K x 8) PARALLEL EEPROM
with SOFTWARE DATA PROTECTION
FAST ACCESS TIME: 90ns
SINGLE 5V ± 10% SUPPLY VOLTAGE
LOW POWER CONSUMPTION
FAST WRITE CYCLE:
– 64 Bytes Page Write Operation
– Byte or Page Write Cycle: 3ms Max
ENHANCED END OF WRITE DETECTION:
– Data Polling
– Toggle Bit
PAGE LOAD TIMER STATUS BIT
HIGH RELIABILITY SINGLE POLYSILICON,
CMOS TECHNOLOGY:
– Endurance >100,000 Erase/Write Cycles
– Data Retention >40 Years
JEDEC APPROVED BYTEWIDE PIN OUT
SOFTWARE DATA PROTECTION
M28C16 is replaced by the products
described on the document M28C16A
DESCRIPTION
The M28C16 is a 2K x 8 low power Parallel
EEPROM fabricatedwith SGS-THOMSON proprie-
tary single polysilicon CMOS technology. The de-
vice offers fast access time with low power
dissipation and requires a 5V power supply. The
circuit has been designed to offer a flexible micro-
controller interface featuring both hardware and
software handshaking with Data Polling and Toggle
Bit. The M28C16 supports 64 byte page write op-
eration. A Software Data Protection (SDP) is also
possible using the standard JEDEC algorithm.
Table 1. Signal Names
A0 - A10 Address Input
DQ0 - DQ7 Data Input / Output
W Write Enable
E Chip Enable
G Output Enable
RB Ready / Busy
VCC Supply Voltage
VSS Ground
NOT FOR NEW DESIGN
24
1
PDIP24 (P)
PLCC32 (K)
24
1
SO24 (MS)
300 mils
TSOP28 (N)
8 x13.4mm
Figure 1. Logic Diagram
VCC
11
A0-A10
8
DQ0-DQ7
W M28C16
E RB *
G
VSS
AI01518B
Note: * RB function is offered only with TSOP28 package.
November 1997
This is information on a product still in production bu t not recommended for new de sign.
1/18

1 page




M28C16 pdf
Figure 5. Software Data Protection Enable Algorithm and Memory Write
Page
Write
Instruction
(Note 1)
WRITE AAh in
Address 555h
WRITE 55h in
Address 2AAh
WRITE A0h in
Address 555h
SDP is set
Page
Write
Instruction
(Note 1)
WRITE AAh in
Address 555h
WRITE 55h in
Address 2AAh
WRITE A0h in
Address 555h
Write Page
(1 up to 64 bytes)
M28C16
WRITE
is enabled
SDP ENABLE ALGORITHM
WRITE IN MEMORY
WHEN SDP IS SET
AI01509B
Note: 1. MSB Address bits (A6 to A10) differ during these specific Page Write operations.
Figure 6. Software Data Protection Disable
Algorithm
Page
Write
Instruction
WRITE AAh in
Address 555h
WRITE 55h in
Address 2AAh
WRITE 80h in
Address 555h
WRITE AAh in
Address 555h
WRITE 55h in
Address 2AAh
WRITE 20h in
Address 555h
Unprotected State
AI01510
Software Data Protection
The M28C16 offers a software controlled write
protection facility that allows the user to inhibit all
write modes to the device including the Chip Erase
instruction. This can be useful in protecting the
memory from inadvertent write cycles that may
occur due to uncontrolled bus conditions.
The M28C16 is shipped as standard in the ”unpro-
tected” state meaning that the memory contents
can be changed as required by the user. After the
Software Data Protection enable algorithm is is-
sued, the device enters the ”Protect Mode” of
operation where no further write commands have
any effect on the memory contents. The device
remains in this mode until a valid Software Data
Protection (SDP) disable sequence is received
whereby the device reverts to its ”unprotected”
state. The Software Data Protection is fully non-
volatile and is not changed by power on/off se-
quences.
To enable the Software Data Protection (SDP) the
device requires the user to write (with a Page Write)
three specific data bytes to three specific memory
locations as per Figure 5. Similarly to disable the
Software Data Protection the user has to write
specific data bytes into six different locations as per
Figure 6 (with a Page Write). This complex series
ensures that the user will never enable or disable
the Software Data Protection accidentally.
5/18

5 Page





M28C16 arduino
Figure 14. Data Polling Waveform Sequence
M28C16
A0-A10
Address of the last byte of the Page Write instruction
E
G
W
DQ7
DQ7
LAST WRITE
DQ7
DQ7
DQ7
INTERNAL WRITE SEQUENCE
DQ7
READY
AI01516
Figure 15. Toggle Bit Waveform Sequence
A0-A10
E
G
W
DQ6
LAST WRITE
(1)
TOGGLE
INTERNAL WRITE SEQUENCE
Note: 1. First Toggle bit is forced to ’0’
READY
AI01517
11/18

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