|
|
PDF M28LV64 Data sheet ( Hoja de datos )
| Número de pieza | M28LV64 | |
| Descripción | 64K (8K x 8) LOW VOLTAGE PARALLEL EEPROM | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de M28LV64 (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
|
No Preview Available !
M28LV64
64K (8K x 8) LOW VOLTAGE PARALLEL EEPROM
with SOFTWARE DATA PROTECTION
FAST ACCESS TIME: 200ns
SINGLE LOW VOLTAGE OPERATION
LOW POWER CONSUMPTION
FAST WRITE CYCLE:
– 64 Bytes Page Write Operation
– Byte or Page Write Cycle: 3ms Max
ENHANCED END OF WRITE DETECTION:
– Ready/Busy Open Drain Output
(only on the M28LV64)
– Data Polling
– Toggle Bit
PAGE LOAD TIMER STATUS BIT
HIGH RELIABILITY SINGLE POLYSILICON,
CMOS TECHNOLOGY:
– Endurance >100,000 Erase/Write Cycles
– Data Retention >40 Years
JEDEC APPROVED BYTEWIDE PIN OUT
SOFTWARE DATA PROTECTION
The M28LV64 is replaced by the
M28C64-xxW
NOT FOR NEW DESIGN
28
1
PDIP28 (P)
PLCC32 (K)
28
1
SO28 (MS)
300 mils
TSOP28 (N)
8 x13.4mm
Figure 1. Logic Diagram
DESCRIPTION
The M28LV64 is an 8K x 8 low power Parallel
EEPROM fabricated with SGS-THOMSON pro-
prietary single polysilicon CMOS technology. The
device offers fast access time with low power dis-
sipation and requires a 2.7V to 3.6V power supply.
VCC
13
A0-A12
8
DQ0-DQ7
Table 1. Signal Names
A0 - A12 Address Input
DQ0 - DQ7 Data Input / Output
W Write Enable
E Chip Enable
G Output Enable
RB Ready / Busy
VCC Supply Voltage
VSS Ground
W M28LV64
E
RB *
G
VSS
AI01538B
Note: * RB function is only available on the M28LV64.
May 1997
This is information on a product still in production bu t not recommended for new de signs.
1/18
1 page  
M28LV64
Microcontroller Control Interface
The M28LV64 provides two write operation status
bits and one status pin that can be used to minimize
the system write cycle. These signals are available
on the I/O port bits DQ7 or DQ6 of the memory
during programming cycle only, or as the RB signal
on a separate pin.
Figure 4. Status Bit Assignment
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
DP TB PLTS Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
DP = Data Polling
TB = Toggle Bit
PLTS = Page Load Timer Status
Data Polling bit (DQ7). During the internal write
cycle, any attempt to read the last byte written will
produce on DQ7 the complementary value of the
previously latched bit. Once the write cycle is fin-
ished the true logic value appears on DQ7 in the
read cycle.
Toggle bit (DQ6). The M28LV64 offers another
way for determining when the internal write cycle
is completed. During the internal Erase/Write cycle,
DQ6 will toggle from ”0” to ”1” and ”1” to ”0” (the
first read value is ”0”) on subsequent attempts to
read the memory. When the internal cycle is com-
pleted the toggling will stop and the device will be
accessible for a new Read or Write operation.
Page Load Timer Status bit (DQ5). In the Page
Write mode data may be latched by E or W up to
100µs after the previous byte. Up to 64 bytes may
be input. The Data output (DQ5) indicates the
status of the internal Page Load Timer. DQ5 may
be read by asserting Output Enable Low (tPLTS).
DQ5 Low indicates the timer is running, High indi-
cates time-out after which the write cycle will start
and no new data may be input.
Ready/Busy pin (available only on the
M28LV64). The RB pin provides a signal at its open
drain output which is low during the erase/write
cycle, but which is released at the completionof the
programming cycle.
Software Data Protection
The M28LV64 offers a software controlled write
protection facility that allows the user to inhibit all
write modes to the device including the Chip Erase
instruction. This can be useful in protecting the
memory from inadvertent write cycles that may
occur due to uncontrolled bus conditions.
The M28LV64is shipped as standard in the ”unpro-
tected” state meaning that the memory contents
can be changed as required by the user. After the
Software Data Protection enable algorithm is is-
sued, the device enters the ”Protect Mode” of
operation where no further write commands have
any effect on the memory contents. The device
remains in this mode until a valid Software Data
Protection (SDP) disable sequence is received
whereby the device reverts to its ”unprotected”
state. The Software Data Protection is fully non-
volatile and is not changed by power on/off se-
quences.
To enable the Software Data Protection (SDP) the
device requires the user to write (with a Page Write)
three specific data bytes to three specific memory
locations as per Figure 5. Similarly to disable the
Software Data Protection the user has to write
specific data bytes into six different locations as per
Figure 6 (with a Page Write). This complex series
ensures that the user will never enable or disable
the Software Data Protection accidentally.
5/18
5 Page 
Figure 12. Page Write Mode AC Waveforms - Write Enable Controlled
M28LV64
A0-A12
Addr 0
Addr 1
Addr 2
Addr n
E
G
W
DQ0-DQ7
tWHWL
tWLWH
Byte 0
Byte 1
tWHWH
Byte 2
DQ5
RB
tWHRL
tPLTS
tWHRH
tWHWH
Byte n
Byte n
AI00752C
Figure 13. Software Protected Write Cycle Waveforms
G
E
W
A0-A5
A6-A12
DQ0-DQ7
tAVEL
tWLWH
tWHWL
tWHWH
tWLAX
Byte Address
tWHDX
1555h
0AAAh
1555h
Page Address
tDVWH
AAh 55h A0h Byte 0
Byte 62
Byte 63
AI01358
Note: A6 through A12 must specify the same page address during each high to low transition of W (or E) after the software code has been
entered. G must be high only when W and E are both low.
11/18
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet M28LV64.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| M28LV64 | 64K (8K x 8) LOW VOLTAGE PARALLEL EEPROM | STMicroelectronics |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |