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PDF M28W160BB Data sheet ( Hoja de datos )
| Número de pieza | M28W160BB | |
| Descripción | 16 Mbit 3V Supply Flash Memory | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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M28W160BT
M28W160BB
16 Mbit (1Mb x16, Boot Block)
3V Supply Flash Memory
FEATURES SUMMARY
s SUPPLY VOLTAGE
– VDD = 2.7V to 3.6V Core Power Supply
– VDDQ= 1.65V to 3.6V for Input/Output
– VPP = 12V for fast Program (optional)
s ACCESS TIME: 70, 85, 90,100ns
s PROGRAMMING TIME
– 10µs typical
– Double Word Programming Option
s COMMON FLASH INTERFACE
– 64 bit Security Code
s MEMORY BLOCKS
– Parameter Blocks (Top or Bottom location)
– Main Blocks
s BLOCK PROTECTION on TWO PARAMETER
BLOCKS
– WP for Block Protection
s AUTOMATIC STAND-BY MODE
s PROGRAM and ERASE SUSPEND
s 100,000 PROGRAM/ERASE CYCLES per
BLOCK
s ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Top Device Code, M28W160BT: 90h
– Bottom Device Code, M28W160BB: 91h
Figure 1. Packages
µBGA
µBGA46 (GB)
6.39 x 6.37mm
FBGA
TFBGA46 (ZB)
6.39 x 6.37mm
TSOP48 (N)
12 x 20mm
May 2002
1/45
1 page  
M28W160BT, M28W160BB
SUMMARY DESCRIPTION
The M28W160B is a 16 Mbit (1 Mbit x 16) non-vol-
atile Flash memory that can be erased electrically
at the block level and programmed in-system on a
Word-by-Word basis. These operations can be
performed using a single low voltage (2.7 to 3.6V)
supply. VDDQ allows to drive the I/O pin down to
1.65V. An optional 12V VPP power supply is pro-
vided to speed up customer programming.
The device features an asymmetrical blocked ar-
chitecture. The M28W160B has an array of 39
blocks: 8 Parameter Blocks of 4 KWord and 31
Main Blocks of 32 KWord. M28W160BT has the
Parameter Blocks at the top of the memory ad-
dress space while the M28W160BB locates the
Parameter Blocks starting from the bottom. The
memory maps are shown in Figure 6, Block Ad-
dresses.
Parameter blocks 0 and 1 can be protected from
accidental programming or erasure. Each block
can be erased separately. Erase can be suspend-
ed in order to perform either read or program in
any other block and then resumed. Program can
be suspended to read data in any other block and
then resumed. Each block can be programmed
and erased over 100,000 cycles.
Program and Erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller takes care of the tim-
ings necessary for program and erase operations.
The end of a program or erase operation can be
detected and any error conditions identified. The
command set required to control the memory is
consistent with JEDEC standards.
The memory is offered in TSOP48 (10 X 20mm),
µBGA46 (6.39 x 6.37mm, 0.75mm pitch) and
TFBGA46 (6.39 x 6.37mm, 0.75mm pitch) packag-
es and is supplied with all the bits erased (set to
’1’).
Figure 2. Logic Diagram
VDD VDDQ VPP
20
A0-A19
16
DQ0-DQ15
W
E M28W160BT
G M28W160BB
RP
WP
VSS
AI02628
Table 1. Signal Names
A0-A19
Address Inputs
DQ0-DQ15 Data Input/Output
E Chip Enable
G Output Enable
W Write Enable
RP Reset
WP Write Protect
VDD Core Power Supply
VDDQ
Power Supply for
Input/Output
VPP
Optional Supply Voltage for
Fast Program & Erase
VSS Ground
5/45
5 Page 
M28W160BT, M28W160BB
BUS OPERATIONS
There are six standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby, Automatic Standby and Re-
set. See Table 2, Bus Operations, for a summary.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.
Read. Read Bus operations are used to output
the contents of the Memory Array, the Electronic
Signature, the Status Register and the Common
Flash Interface. Both Chip Enable and Output En-
able must be at VIL in order to perform a read op-
eration. The Chip Enable input should be used to
enable the device. Output Enable should be used
to gate data onto the output. The data read de-
pends on the previous command written to the
memory (see Command Interface section). See
Figure 9, Read Mode AC Waveforms, and Table
12, Read AC Characteristics, for details of when
the output becomes valid.
Read mode is the default state of the device when
exiting Reset or after power-up.
Write. Bus Write operations write Commands to
the memory or latch Input Data to be programmed.
A write operation is initiated when Chip Enable
and Write Enable are at VIL with Output Enable at
VIH. Commands, Input Data and Addresses are
latched on the rising edge of Write Enable or Chip
Enable, whichever occurs first.
Table 2. Bus Operations
Operation
E
G
Read
VIL VIL
Write
VIL VIH
Output Disable VIL VIH
Standby
VIH X
Reset
XX
Note: X = VIL or VIH, VPPH = 12V ± 5%.
W
VIH
VIL
VIH
X
X
See Figures 10 and 11, Write AC Waveforms, and
Tables 13 and 14, Write AC Characteristics, for
details of the timing requirements.
Output Disable. The data outputs are high im-
pedance when the Output Enable is at VIH.
Standby. Standby disables most of the internal
circuitry allowing a substantial reduction of the cur-
rent consumption. The memory is in stand-by
when Chip Enable is at VIH and the device is in
read mode. The power consumption is reduced to
the stand-by level and the outputs are set to high
impedance, independently from the Output Enable
or Write Enable inputs. If Chip Enable switches to
VIH during a program or erase operation, the de-
vice enters Standby mode when finished.
Automatic Standby. Automatic Standby pro-
vides a low power consumption state during Read
mode. Following a read operation, the device en-
ters Automatic Standby after 150ns of bus inactiv-
ity, even if Chip Enable is low, VIL, and the supply
current is reduced to IDD1. The data Inputs/Out-
puts will still output data.
Reset. During Reset mode, when Output Enable
is low, VIL, the memory is deselected and the out-
puts are high impedance. The memory is in Reset
mode when Reset is at VIL. The power consump-
tion is reduced to the Standby level, independently
from the Chip Enable, Output Enable or Write En-
able inputs. If Reset is pulled to VSS during a Pro-
gram or Erase, this operation is aborted and the
memory content is no longer valid.
RP WP
VPP DQ0-DQ15
VIH
X
Don't Care
Data Output
VIH
X
VDD or VPPH
Data Input
VIH X Don't Care
Hi-Z
VIH X Don't Care
Hi-Z
VIL X Don't Care
Hi-Z
11/45
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