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PDF M28W320CT Data sheet ( Hoja de datos )

Número de pieza M28W320CT
Descripción 32 Mbit 3V Supply Flash Memory
Fabricantes STMicroelectronics 
Logotipo STMicroelectronics Logotipo



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M28W320CT
M28W320CB
32 Mbit (2Mb x16, Boot Block)
3V Supply Flash Memory
FEATURES SUMMARY
s SUPPLY VOLTAGE
– VDD = 2.7V to 3.6V Core Power Supply
– VDDQ= 1.65V to 3.6V for Input/Output
– VPP = 12V for fast Program (optional)
s ACCESS TIME: 70, 85, 90,100ns
s PROGRAMMING TIME:
– 10µs typical
– Double Word Programming Option
s COMMON FLASH INTERFACE
– 64 bit Security Code
s MEMORY BLOCKS
– Parameter Blocks (Top or Bottom location)
– Main Blocks
s BLOCK LOCKING
– All blocks locked at Power Up
– Any combination of blocks can be locked
– WP for Block Lock-Down
s SECURITY
– 64 bit user Programmable OTP cells
– 64 bit unique device identifier
– One Parameter Block Permanently Lockable
s AUTOMATIC STAND-BY MODE
s PROGRAM and ERASE SUSPEND
s 100,000 PROGRAM/ERASE CYCLES per
BLOCK
s ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Top Device Code, M28W320CT: 88BAh
– Bottom Device Code, M28W320CB: 88BBh
Figure 1. Packages
µBGA
µBGA47 (GB)
6.39 x 10.5mm
FBGA
TFBGA47 (ZB)
6.39 x 10.5mm
TSOP48 (N)
12 x 20mm
May 2002
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M28W320CT pdf
M28W320CT, M28W320CB
SUMMARY DESCRIPTION
The M28W320C is a 32 Mbit (2 Mbit x 16) non-vol-
atile Flash memory that can be erased electrically
at the block level and programmed in-system on a
Word-by-Word basis. These operations can be
performed using a single low voltage (2.7 to 3.6V)
supply. VDDQ allows to drive the I/O pin down to
1.65V. An optional 12V VPP power supply is pro-
vided to speed up customer programming.
The device features an asymmetrical blocked ar-
chitecture. The M28W320C has an array of 71
blocks: 8 Parameter Blocks of 4 KWord and 63
Main Blocks of 32 KWord. M28W320CT has the
Parameter Blocks at the top of the memory ad-
dress space while the M28W320CB locates the
Parameter Blocks starting from the bottom. The
memory maps are shown in Figure 6, Block Ad-
dresses.
The M28W320C features an instant, individual
block locking scheme that allows any block to be
locked or unlocked with no latency, enabling in-
stant code and data protection. All blocks have
three levels of protection. They can be locked and
locked-down individually preventing any acciden-
tal programming or erasure. There is an additional
hardware protection against program and erase.
When VPP VPPLK all blocks are protected against
program or erase. All blocks are locked at Power
Up.
Each block can be erased separately. Erase can
be suspended in order to perform either read or
program in any other block and then resumed.
Program can be suspended to read data in any
other block and then resumed. Each block can be
programmed and erased over 100,000 cycles.
The device includes a 128 bit Protection Register
and a Security Block to increase the protection of
a system design. The Protection Register is divid-
ed into two 64 bit segments, the first one contains
a unique device number written by ST, while the
second one is one-time-programmable by the us-
er. The user programmable segment can be per-
manently protected. The Security Block,
parameter block 0, can be permanently protected
by the user. Figure 7, shows the Security Block
and Protection Register Memory Map.
Program and Erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller takes care of the tim-
ings necessary for program and erase operations.
The end of a program or erase operation can be
detected and any error conditions identified. The
command set required to control the memory is
consistent with JEDEC standards.
The memory is offered in TSOP48 (10 X 20mm),
µGBA47 (6.39 x 10.5mm, 0.75mm pitch) and
TFBGA47 (6.39 x 10.5mm, 0.75mm pitch) packag-
es and is supplied with all the bits erased (set to
’1’).
Figure 2. Logic Diagram
VDD VDDQ VPP
21
A0-A20
W
E
G
RP
WP
16
DQ0-DQ15
M28W320CT
M28W320CB
VSS
AI03521
Table 1. Signal Names
A0-A20
Address Inputs
DQ0-DQ15 Data Input/Output
E Chip Enable
G Output Enable
W Write Enable
RP Reset
WP Write Protect
VDD Core Power Supply
VDDQ
Power Supply for
Input/Output
VPP
Optional Supply Voltage for
Fast Program & Erase
VSS Ground
NC Not Connected Internally
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M28W320CT arduino
M28W320CT, M28W320CB
BUS OPERATIONS
There are six standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby, Automatic Standby and Re-
set. See Table 2, Bus Operations, for a summary.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.
Read. Read Bus operations are used to output
the contents of the Memory Array, the Electronic
Signature, the Status Register and the Common
Flash Interface. Both Chip Enable and Output En-
able must be at VIL in order to perform a read op-
eration. The Chip Enable input should be used to
enable the device. Output Enable should be used
to gate data onto the output. The data read de-
pends on the previous command written to the
memory (see Command Interface section). See
Figure 10, Read Mode AC Waveforms, and Table
15, Read AC Characteristics, for details of when
the output becomes valid.
Read mode is the default state of the device when
exiting Reset or after power-up.
Write. Bus Write operations write Commands to
the memory or latch Input Data to be programmed.
A write operation is initiated when Chip Enable
and Write Enable are at VIL with Output Enable at
VIH. Commands, Input Data and Addresses are
latched on the rising edge of Write Enable or Chip
Enable, whichever occurs first.
See Figures 11 and 12, Write AC Waveforms, and
Tables 16 and 17, Write AC Characteristics, for
details of the timing requirements.
Output Disable. The data outputs are high im-
pedance when the Output Enable is at VIH.
Standby. Standby disables most of the internal
circuitry allowing a substantial reduction of the cur-
rent consumption. The memory is in stand-by
when Chip Enable is at VIH and the device is in
read mode. The power consumption is reduced to
the stand-by level and the outputs are set to high
impedance, independently from the Output Enable
or Write Enable inputs. If Chip Enable switches to
VIH during a program or erase operation, the de-
vice enters Standby mode when finished.
Automatic Standby. Automatic Standby pro-
vides a low power consumption state during Read
mode. Following a read operation, the device en-
ters Automatic Standby after 150ns of bus inactiv-
ity even if Chip Enable is Low, VIL, and the supply
current is reduced to IDD1. The data Inputs/Out-
puts will still output data if a bus Read operation is
in progress.
Reset. During Reset mode when Output Enable
is Low, VIL, the memory is deselected and the out-
puts are high impedance. The memory is in Reset
mode when Reset is at VIL. The power consump-
tion is reduced to the Standby level, independently
from the Chip Enable, Output Enable or Write En-
able inputs. If Reset is pulled to VSS during a Pro-
gram or Erase, this operation is aborted and the
memory content is no longer valid.
Table 2. Bus Operations
Operation
E
G
W RP WP
VPP DQ0-DQ15
Bus Read
VIL VIL VIH VIH
X
Don't Care
Data Output
Bus Write
VIL VIH VIL VIH
X
VDD or VPPH
Data Input
Output Disable VIL VIH VIH VIH X Don't Care
Hi-Z
Standby
VIH X
X VIH X Don't Care
Hi-Z
Reset
X
Note: X = VIL or VIH, VPPH = 12V ± 5%.
X
X VIL X Don't Care
Hi-Z
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