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PDF CAT28F020 Data sheet ( Hoja de datos )
| Número de pieza | CAT28F020 | |
| Descripción | 2 Megabit CMOS Flash Memory | |
| Fabricantes | Catalyst Semiconductor | |
| Logotipo |  |
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CAT28F020
2 Megabit CMOS Flash Memory
Licensed Intel
second source
FEATURES
s Fast read access time: 90/120 ns
s Low power CMOS dissipation:
– Active: 30 mA max (CMOS/TTL levels)
– Standby: 1 mA max (TTL levels)
– Standby: 100 µA max (CMOS levels)
s High speed programming:
– 10 µs per byte
– 4 seconds typical chip program
s 0.5 seconds typical chip-erase
s 12.0V ± 5% programming and erase voltage
DESCRIPTION
The CAT28F020 is a high speed 256K x 8-bit electrically
erasable and reprogrammable Flash memory ideally
suited for applications requiring in-system or after-sale
code updates. Electrical erasure of the full memory
contents is achieved typically within 0.5 second.
It is pin and Read timing compatible with standard
EPROM and E2PROM devices. Programming and
Erase are performed through an operation and verify
algorithm. The instructions are input via the I/O bus,
s Commercial, industrial and automotive
temperature ranges
s Stop timer for program/erase
s On-chip address and data latches
s JEDEC standard pinouts:
– 32-pin DIP
– 32-pin PLCC
– 32-pin TSOP (8 x 20)
s 100,000 program/erase cycles
s 10 year data retention
s Electronic signature
using a two write cycle scheme. Address and Data are
latched to free the I/O bus and address bus during the
write operation.
The CAT28F020 is manufactured using Catalyst’s
advanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 32-pin plastic DIP, 32-pin PLCC or 32-pin
TSOP packages.
BLOCK DIAGRAM
I/O0–I/O7
ERASE VOLTAGE
SWITCH
I/O BUFFERS
WE
CE
OE
A0–A17
COMMAND
REGISTER
PROGRAM VOLTAGE
SWITCH
CE, OE LOGIC
DATA SENSE
LATCH AMP
VOLTAGE VERIFY
SWITCH
Y-DECODER
X-DECODER
Y-GATING
2,097,152 BIT
MEMORY
ARRAY
5115 FHD F02
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1029, Rev. B
1 page  
CAT28F020
SUPPLY CHARACTERISTICS
Symbol
Parameter
Min Typ Max Unit
VCC
VCC Supply Voltage
28F020-90
28F020-12
4.75
4.5
5.5 V
5.5 V
VPPL
VPP During Read Operations
0
6.5 V
VPPH VPP During Read/Erase/Program
11.4
12.6 V
A.C. CHARACTERISTICS, Read Operation
VCC = +5V ±10%, unless otherwise specified. (See Note 8)
JEDEC Standard
Symbol Symbol
tAVAV
tRC
tELQV
tCE
tAVQV
tACC
tGLQV
tOE
tAXQX
tGLQX
tELQX
tGHQZ
tEHQZ
tWHGL(1)
tOH
tOLZ(1)(6)
tLZ(1)(6)
tDF(1)(2)
tDF(1)(2)
-
Parameter
28F020-90(7)
Min Typ Max
Read Cycle Time
90
CE Access Time
90
Address Access Time
90
OE Access Time
35
Output Hold from Address OE/CE Change 0
OE to Output in Low-Z
0
CE to Output in Low-Z
0
OE High to Output High-Z
30
CE High to Output High-Z
40
Write Recovery Time Before Read
6
28F020-12(7)
Min Typ Max
120
120
120
50
0
0
0
30
40
6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
Figure 1. A.C. Testing Input/Output Waveform(3)(4)(5)
2.4 V
0.45 V
INPUT PULSE LEVELS
2.0 V
0.8 V
REFERENCE POINTS
Testing Load Circuit (example)
1.3V
1N914
3.3K
DEVICE
UNDER
TEST
OUT
CL = 100 pF
Note:
CL INCLUDES JIG CAPACITANCE
1. This parameter is tested initially and after a design or process change that affects the parameter.
2. Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer.
3. Input Rise and Fall Times (10% to 90%) < 10 ns.
4. Input Pulse Levels = 0.45 V and 2.4 V. For High Speed Input Pulse Levels 0.0 V and 3.0 V.
5. Input and Output Timing Reference = 0.8 V and 2.0 V. For High Speed Input and Output Timing Reference = 1.5 V.
6. Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid.
7. For load and reference points, see Fig. 1.
8. CAT28F020-90, VCCMIN = 4.75 V.
5 Doc. No. 1029, Rev. B
5 Page 
CAT28F020
Erase-Verify Mode
The Erase-verify operation is performed on every byte
after each erase pulse to verify that the bits have been
erased.
Programming Mode
The programming operation is initiated using the pro-
gramming algorithm of Figure 7. During the first write
cycle, the command 40H is written into the command
register. During the second write cycle, the address of
the memory location to be programmed is latched on the
falling edge of WE, while the data is latched on the rising
edge of WE. The program operation terminates with the
next rising edge of WE. An integrated stop timer allows
for automatic timing control over this operation, eliminat-
ing the need for a maximum program timing specifica-
tion. Refer to AC Characteristics (Program/Erase) for
specific timing parameters.
Program-Verify Mode
A Program-verify cycle is performed to ensure that all
bits have been correctly programmed following each
byte programming operation. The specific address is
already latched from the write cycle just completed, and
stays latched until the verify is completed. The Program-
verify operation is initiated by writing C0H into the
command register. An internal reference generates the
necessary high voltages so that the user does not need
to modify VCC. Refer to AC Characteristics (Program/
Erase) for specific timing parameters.
Figure 6. A.C. Timing for Programming Operation
VCC POWER-UP SETUP PROGRAM LATCH ADDRESS
& STANDBY
COMMAND
& DATA
PROGRAM
VERIFY
PROGRAMMING COMMAND
PROGRAM VCC POWER-DOWN/
VERIFICATION
STANDBY
ADDRESSES
tWC
tWC
tAS tAH
CE (E)
tCS
tCH
tCH
tCS
tCH
OE (G)
tGHWL
tWPH
tWHWH1
tWHGL
WE (W)
DATA (I/O)
tWP
tDS
HIGH-Z
DATA IN
= 40H
tDH
tDS
tWP
DATA IN
tDH
VCC 5.0V
0V
VPP VPPH
VPPL
tVPEL
tWP
tDS
tDH
DATA IN
= C0H
tOE
tOLZ
tLZ
tCE
tRC
tEHQZ
tDF
tOH
VALID
DATA OUT
28F020 F07
11 Doc. No. 1029, Rev. B
11 Page | ||
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