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PDF DT28F016SV Data sheet ( Hoja de datos )

Número de pieza DT28F016SV
Descripción 16-MBIT MEMORY
Fabricantes Intel 
Logotipo Intel Logotipo



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E
28F016SV
16-MBIT (1 MBIT x 16, 2 MBIT x 8)
FlashFile™ MEMORY
Includes Commercial and Extended Temperature Specifications
n SmartVoltage Technology
User-Selectable 3.3V or 5V VCC
User-Selectable 5V or 12V VPP
n 65 ns Access Time
n 1 Million Erase Cycles per Block
n 30.8 MB/sec Burst Write Transfer Rate
n 0.48 MB/sec Sustainable Write Transfer
Rate
n Configurable x8 or x16 Operation
n 56-Lead TSOP and SSOP Type I
Packages
n Backwards-Compatible with 28F016SA,
28F008SA Command Set
n Revolutionary Architecture
Multiple Command Execution
Program during Erase
Command Super-Set of the Intel
28F008SA
Page Buffer Program
n 2 µA Typical Deep Power-Down
n 32 Independently Lockable Blocks
n State-of-the-Art 0.6 µm ETOX™ IV Flash
Technology
Intel’s 28F016SV 16-Mbit FlashFile™ memory is a revolutionary architecture which is the ideal choice for
designing embedded direct-execute code and mass storage data/file flash memory systems. With innovative
capabilities, low-power operation, user-selectable VPP voltage and high read/program performance, the
28F016SV enables the design of truly mobile, high-performance personal computing and communications
products.
The 28F016SV is the highest density, highest performance nonvolatile read/program solution for solid-state
storage applications. Its symmetrically-blocked architecture (100% compatible with the 28F008SA 8-Mbit and
28F016SA 16-Mbit FlashFile memories), extended cycling, flexible VCC and VPP voltage (SmartVoltage
technology), fast program and read performance and selective block locking, provide a highly-flexible memory
component suitable for Resident Flash Arrays, high-density memory cards and PCMCIA-ATA flash drives.
The 28F016SV’s dual read voltage enables the design of memory cards which can be read/written in 3.3V
and 5V systems interchangeably. Its x8/x16 architecture allows optimization of the memory-to-processor
interface. The flexible block locking option enables bundling of executable application software in a Resident
Flash Array or memory card. The 28F016SV is manufactured on Intel’s 0.6 µm ETOX IV process technology.
July 1997
Order Number: 290528-007
7/11/97 11:03 AM 29052807.DOC

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DT28F016SV pdf
E
28F016SV FlashFile™ MEMORY
Number
-004
-005
-006
-007
REVISION HISTORY (Continued)
Description
Added 3/5# pin to Block Diagram (Figure 1), Pinout Configurations (Figures 2 and 3),
Product Overview (Section 1.1) and Lead Descriptions (Section 2.1)
Added 3/5# pin to Test Conditions of ICCS Specifications
Added 3/5# pin (Y) to Timing Nomenclature (Section 5.5)
Increased tPHQV Specifications at 5V VCC to 400 ns for E28F016SV 065 devices
and 480 ns for E28F106SV 070 devices.
Modified Power-Up and Reset Timings (Section 5.9) to include 3/5# pin: Removed t5VPH
and t3VPH specifications; Added tPLYL, tPLYH, tYLPH, and tYHPH specifications
Added tPHEL3 and tPHEL5 specifications to Power-Up and Reset Timings (Section 5.9)
Corrected TSOP Mechanical Specification A1 from 0.50 mm to 0.050 mm (Section 6.0)
Corrected SSOP Mechanical Spec. B (max) from 0.20 mm to 0.40 mm (Section 6.0)
Minor cosmetic changes throughout document.
Updated DC Specifications: ICCD, IPPES
Updated AC Specifications: Page Buffer Reads: (tAVAV, tAVQV, tELQV, and tFLQV/tFHQV)
Page Buffer WE#-Controlled Command Writes (tELWL)
CE#-Controlled Command Write Parameters (tAVAV, tELEH, tEHEL)
Combined Commercial and Extended Temperature information into single datasheet.
Updated AC Specifications: Page Buffer Reads: (tAVAV, tAVQV, tELQV, and tFLQV/tFHQV)
Updated Disclaimer
5

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DT28F016SV arduino
E
28F016SV FlashFile™ MEMORY
2.1 Lead Descriptions
Symbol
Type
Name and Function
A0
INPUT
BYTE-SELECT ADDRESS: Selects between high and low byte when
device is in x8 mode. This address is latched in x8 data programs. Not
used in x16 mode (i.e., the A0 input buffer is turned off when BYTE# is
high).
A1–A15
INPUT
WORD-SELECT ADDRESSES: Select a word within one 64-Kbyte block.
A6–15 selects 1 of 1024 rows, and A1–5 selects 16 of 512 columns. These
addresses are latched during data programs.
A16–A20
INPUT
BLOCK-SELECT ADDRESSES: Select 1 of 32 Erase blocks. These
addresses are latched during data programs, erase and lock block
operations.
DQ0–DQ7
INPUT/OUTPUT
LOW-BYTE DATA BUS: Inputs data and commands during CUI program
cycles. Outputs array, buffer, identifier or status data in the appropriate
read mode. Floated when the chip is de-selected or the outputs are
disabled.
DQ8–DQ15
INPUT/OUTPUT
HIGH-BYTE DATA BUS: Inputs data during x16 data program
operations. Outputs array, buffer or identifier data in the appropriate read
mode; not used for Status Register reads. Floated when the chip is de-
selected or the outputs are disabled.
CE0#, CE1#
RP#
INPUT
INPUT
CHIP ENABLE INPUTS: Activate the device’s control logic, input buffers,
decoders and sense amplifiers. With either CE0# or CE1# high, the device
is de-selected and power consumption reduces to standby levels upon
completion of any current data program or erase operations. Both CE0#
and CE1# must be low to select the device.
All timing specifications are the same for both signals. Device Selection
occurs with the latter falling edge of CE0# or CE1#. The first rising edge of
CE0# or CE1# disables the device.
RESET/POWER-DOWN: RP# low places the device in a deep power-
down state. All circuits that consume static power, even those circuits
enabled in standby mode, are turned off. When returning from deep
power-down, a recovery time of tPHQV is required to allow these circuits to
power-up.
When RP# goes low, any current or pending WSM operation(s) are
terminated, and the device is reset. All Status Registers return to ready
(with all status flags cleared).
Exit from deep power-down places the device in read array mode.
OE#
INPUT
OUTPUT ENABLE: Gates device data through the output buffers when
low. The outputs float to tri-state off when OE# is high.
NOTE:
CEx# overrides OE#, and OE# overrides WE#.
WE#
INPUT
WRITE ENABLE: Controls access to the CUI, Page Buffers, Data Queue
Registers and Address Queue Latches. WE# is active low, and latches
both address and data (command or array) on its rising edge.
Page Buffer addresses are latched on the falling edge of WE#.
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