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PDF R0929LC12C Data sheet ( Hoja de datos )

Número de pieza R0929LC12C
Descripción Distributed Gate Thyristor
Fabricantes IXYS 
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Date:- 2 August 2012
Data Sheet Issue:- 2
Distributed Gate Thyristor
Types R0929LC10x to R0929LC12x
Absolute Maximum Ratings
VDRM
VDSM
VRRM
VRSM
VOLTAGE RATINGS
Repetitive peak off-state voltage, (note 1)
Non-repetitive peak off-state voltage, (note 1)
Repetitive peak reverse voltage, (note 1)
Non-repetitive peak reverse voltage, (note 1)
MAXIMUM
LIMITS
1000-1200
1000-1200
1000-1200
1100-1300
UNITS
V
V
V
V
IT(AV)
IT(AV)
IT(AV)
IT(RMS)
IT(d.c.)
ITSM
ITSM2
I2t
I2t
(di/dt)cr
VRGM
PG(AV)
PGM
VGD
THS
Tstg
OTHER RATINGS
Mean on-state current, Tsink=55°C, (note 2)
Mean on-state current. Tsink=85°C, (note 2)
Mean on-state current. Tsink=85°C, (note 3)
Nominal RMS on-state current, Tsink=25°C, (note 2)
D.C. on-state current, Tsink=25°C, (note 4)
Peak non-repetitive surge tp=10ms, VRM=0.6VRRM, (note 5)
Peak non-repetitive surge tp=10ms, VRM10V, (note 5)
I2t capacity for fusing tp=10ms, VRM=0.6VRRM, (note 5)
I2t capacity for fusing tp=10ms, VRM10V, (note 5)
Maximum rate of rise of on-state current (repetitive), (Note 6)
Maximum rate of rise of on-state current (non-repetitive), (Note 6)
Peak reverse gate voltage
Mean forward gate power
Peak forward gate power
Non-trigger gate voltage, (Note 7)
Operating temperature range
Storage temperature range
Notes:-
1) De-rating factor of 0.13% per °C is applicable for Tj below 25°C.
2) Double side cooled, single phase; 50Hz, 180° half-sinewave.
3) Single side cooled, single phase; 50Hz, 180° half-sinewave.
4) Double side cooled.
5) Half-sinewave, 125°C Tj initial.
6) VD=67% VDRM, IFG=2A, tr0.5µs, Tcase=125°C.
7) Rated VDRM.
MAXIMUM
LIMITS
929
603
339
1893
1505
9.0
9.9
405×103
490×103
1000
1500
5
2
30
0.25
-40 to +125
-40 to +150
UNITS
A
A
A
A
A
kA
kA
A2s
A2s
A/µs
A/µs
V
W
W
V
°C
°C
Data Sheet R0929LC10x to R0929LC12x Issue 2
Page 1 of 12
August 2012

1 page




R0929LC12C pdf
Distributed gate thyristor R0929LC10x to R0929LC12x
The total dissipation is now given by:
W(TOT) = W(original) + E f
12.2 Determination without Measurement
In circumstances where it is not possible to measure voltage and current conditions, or for design
purposes, the additional losses E in joules may be estimated as follows.
Let E be the value of energy per reverse cycle in joules (curves in Figure 9).
Let f be the operating frequency in Hz
( )TSINK (new) = TSINK (original ) E Rth f
Where TSINK (new) is the required maximum heat sink temperature and
TSINK (original) is the heat sink temperature given with the frequency ratings.
A suitable R-C snubber network is connected across the thyristor to restrict the transient reverse voltage
to a peak value (Vrm) of 67% of the maximum grade. If a different grade is being used or Vrm is other than
67% of Grade, the reverse loss may be approximated by a pro rata adjustment of the maximum value
obtained from the curves.
NOTE 1- Reverse Recovery Loss by Measurement
This thyristor has a low reverse recovered charge and peak reverse recovery current. When measuring
the charge care must be taken to ensure that:
(a) a.c. coupled devices such as current transformers are not affected by prior passage of high
amplitude forward current.
(b) A suitable, polarised, clipping circuit must be connected to the input of the measuring oscilloscope
to avoid overloading the internal amplifiers by the relatively high amplitude forward current signal
(c) Measurement of reverse recovery waveform should be carried out with an appropriate critically
damped snubber, connected across diode anode to cathode. The formula used for the calculation
of this snubber is shown below:
R2 = 4 Vr
CS
di
dt
Where: Vr = Commutating source voltage
CS = Snubber capacitance
R = Snubber resistance
13.0 Gate Drive
The recommended pulse gate drive is 30V, 15with a short-circuit current rise time of not more than
0.5µs. This gate drive must be applied when using the full di/dt capability of the device.
The duration of pulse may need to be configured with respect to the application but should be no shorter
than 20µs, otherwise an increase in pulse current could be needed to supply the resulting increase in
charge to trigger.
Data Sheet R0929LC10x to R0929LC12x Issue 2
Page 5 of 12
August 2012

5 Page





R0929LC12C arduino
Distributed gate thyristor R0929LC10x to R0929LC12x
Figure 17 - Square wave energy per pulse
1.00E+03
RR0902992L9SL1C01x0-x1-21x2x
IsIssuseue1 2
di/dt=100A/µs
Tj=125°C
1.00E+02
Figure 18 - Square wave energy per pulse
1.00E+03
RR0902992L9SLC101x0-x1-21x2x
IsIssuseue12
di/dt=500A/µs
Tj=125°C
1.00E+02
1.00E+01
1.00E+01
4kA
2kA
4kA
1.00E+00
2kA
1.5kA
1kA
1.00E-01
500A
1.00E+00
1.00E-01
1.5kA
1kA
500A
1.00E-02
1.00E-05
1.00E-04
1.00E-03
Pulse width (s)
1.00E-02
1.00E-02
1.00E-05
1.00E-04
1.00E-03
Pulse width (s)
1.00E-02
Figure 19 - Maximum surge and I2t Ratings
100000
Gate may temporarily lose control of conduction angle
R00992299LLCS1100xx-1-122xx
IIssssuuee21
Tj (initial) = 125°C
1.00E+07
I2t: VRRM10V
I2t: 60% VRRM
10000
1.00E+06
ITSM: VRRM10V
ITSM: 60% VRRM
1000
1
3 5 10
Duration of surge (ms)
1
5 10
50 100
Duration of surge (cycles @ 50Hz)
1.00E+05
Data Sheet R0929LC10x to R0929LC12x Issue 2
Page 11 of 12
August 2012

11 Page







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