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PDF W83759A Data sheet ( Hoja de datos )

Número de pieza W83759A
Descripción ADVANCED VL-IDE DISK CONTROLLER
Fabricantes Winbond 
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W83759A
ADVANCED VL-IDE DISK CONTROLLER
GENERAL DESCRIPTION
The W83759A is an advanced version of Winbond's popular VL-IDE interface chip, the W83759. The
W83759A retains all of the features and compatibility of the W83759 (the chip meets the ANSI ATA
4.0 specification for IDE hard disk operation and the VESA VL-Bus 2.0 specification for PC local bus
devices) while incorporating new features to meet Enhanced IDE, SFF-8011, ATA-2, and Fast-ATA
specifications.
Supports Disk Capacity of Greater than 528 MB
The W83759A's driver can handle remapping from BIOS CHS mode to HDD LBA mode. This scheme
enables users to break the 528 MB per drive barrier, allowing full use of BIOS INT13 CHS information
in drives with a capacity of up to 8.4 GB.
High Speed Host Transfer Rate
The W83759A supports Enhanced IDE PIO mode 3 and Fast ATA PIO mode 3 and 4 timing; jumper
settings or driver programming can be used to select the PIO mode and a 33 or 50 MHz VL-Bus
clock. Different programming timing can be selected for different drives in the same system. The
burst transfer rate is shown in the following table.
ATA PIO
MODE
0
1
2
3
4
IDE COMMAND CYCLE
TIME (nS)
600
383
240
180
120
BURST TRANSFER
RATE (MB/sec)
3.33
5.22
8.33
11.1
16.6
IORDY THROTTLE
CONTROL
Option
Option
Option
Required
Required
Dual IDE Channels
Like the W83759, the W83759A supports a secondary IDE address (170h-177h/376h) and IRQ15 for
applications with four hard disk drives. Additionally, the primary and secondary channels can be
independently enabled or disabled by jumper settings or software programming.
Non-disk IDE Peripherals
Because the command cycle can be programmed individually for each drive and dual IDE channels
are supported, non-disk IDE peripherals (such as an ATAPI CD-ROM or tape drive) can be attached
to the secondary IDE without affecting the transfer rate of the ATA disk drive. Sales of ATAPI IDE
CD-ROMs are expected to grow rapidly as these devices become a standard part of many users'
desktop PC setup.
Publication Release Date: May 1995
- 1 - Revision A1

1 page




W83759A pdf
W83759A
PIN DESCRIPTION
SYMBOL PIN TYPE
DESCRIPTION
VL-Bus Interface
ADV
LCLK
100 I-PU Advanced mode indicator.
When high, chip is in W83759A mode. When low, chip is in
W83759 mode.
89 I VL-Bus clock.
SYSRST 99
I System reset.
When active, the power-on setting pin acts as input.
LADS
IORDY
/ HDC
HMIO
HWR
BE2
BE0
95 I Address data strobe.
An active low input signal indicates that there is a valid address
and command on the bus.
98 I In W83759A mode: Enhanced IDE IORDY flow control input. Used
to throttle disk's PIO data transfers to improve PIO mode.
In W83759 mode: Host data or code status. Used to distinguish
between IO and interrupt or halt cycles.
97 I-PU Host memory or I/O status.
Used to distinguish between memory and I/O cycles.
96 I Host write or read status.
Used to distinguish between write and read cycles.
1 I Byte enable bits 2 and 0 from the host CPU address bus.
2 These active low inputs specify which bytes will be valid for host
read and write data transfers. When BE2 is low, the host performs
a 32-bit hard disk data transfer cycle when LDEV is active.
LDEV 92 O Local device.
An active low output signal which indicates that the current host
CPU command cycle is a valid W83759A I/O address (1F0h or
170h).
LRDY
93 Tri-O Local ready.
An active low output that indicates when a CPU transfer has been
completed. During a cycle LRDY will first be enabled and driven
high. When the cycle is completed, LRDY will immediately be
pulled low and will remain active for one T-state. Then it will drive
high for one T-state before finally being disabled to end the
sequence.
This signal is shared with all other VL-Bus targets and driven by
W83759A only during cycles W83759A has claimed as its own.
Publication Release Date: May 1995
- 5 - Revision A1

5 Page





W83759A arduino
W83759A
CONFIGURATION REGISTERS
Several configuration registers are implemented in the W83759A. These registers are accessible in
single-chip mode through the index/data port. The index/data port address is 1B4h/1B8h or
134h/138h, depending on whether pin IDD0 is high or low at power-on.
When the W83759A is in multi-chip mode (IDD1 is low at power-on setting), an ID code should be
written to 1B0h/130h (IDIN port). The W83759A will then enter the programming sequence if the ID
code matches the chip ID (determined by IDD2, IDD3 at power-on setting) or leave the programming
sequence if the ID code does not match. After the chip has entered the programming sequence, the
chip ID can be read by reading 1BCh/13Ch (IDOUT port).
IDD0_P is HIGH
IDD0_P is LOW
IDIN port (W/O)
1B0h*
130h**
Index port (R/W)
1B4h
134h
data port (R/W)
1B8h
138h
IDOUT port (R/O)
1BCh
13Ch
* The alias base addresses of 1B0h are XB0h and YB0h, where "X" means 0, 4, 8, C and "Y" means 1, 5, 9, D.
** The alias base addresses of 130h are X30h and Y30h, where "X" means 0, 4, 8, C and "Y" means 1, 5, 9, D.
Index map of configuration registers:
INDEX
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
80h(R/O)
POSS1
81h(R/W)
POSP1
82h(R/O)
POSS2
83h(R/W)
POSP2
84h(R/O)
POSS3
85h(R/W)
POSP3
86h(R/W)
ALTCTL
87h(R/O)
REVID
88h(R/W)
PD0TIM0
89h(R/W)
PD0TIM1
8Ah(R/W)
PD1TIM0
8Bh(R/W)
PD1TIM1
8Ch(R/W)
SD0TIM0
8Dh(R/W)
SD0TIM1
8Eh(R/W)
SD1TIM0
8Fh(R/W)
SD1TIM1
ADV
SP1
MD1
MD0
PRDYEN
ADV_P
SP1_P
MD1_P
MD0_P PRDYEN_P
PD0LEN
PD1LEN
SD0LEN
SD1LEN
DSL1
PD0LE_P PD1LEN_P SD0LEN_P SD1LEN_P DSL1_P
PD0EM# PD1EM# SD0EM# SD1EM#
SUSPEN
PD0EM#_P PD1EM#_P SD0EM#_P SD1EM#_P SUSPEN_P
DMASL#_
P
DMASL#
Reserved
Reserved
EMD1
PDRV
EMD0
SDRV
PEMD1_P
Rev 3
PD0ACT3 PD0ACT2 PD0ACT1 PD0ACT0 PD0RCV3
PD0AST1 PD0AST0 PD0DHT1 PD0DHT0 PD0PRE#
PD1ACT3 PD1ACT2 PD1ACT1 PD1ACT0 PD1RCV3
PD1AST1 PD1AST0 PD1DHT1 PD1DHT0 PD1PRE#
SD0ACT3 SD0ACT2 SD0ACT1 SD0ACT0 SD0RCV3
SD0AST1 SD0AST0 SD0DHT1 SD0DHT0 SD0PRE#
SD1ACT3 SD1ACT2 SD1ACT1 SD1ACT0 SD1RCV3
SD1AST1 SD1AST0 SD1DHT1 SD1DHT0 SD1PRE#
Bit 2
SRDYEN
SRDYEN_P
DSL0
DSL0_P
STBY#
STBY#_P
PEMD0_P
Rev 2
PD0RCV2
PD0DMA#
PD1RCV2
PD1DMA#
SD0RCV2
SD0DMA#
SD1RCV2
SD1DMA#
Bit 1
IDEN1
IDEN1_P
CRLK#
CRLK#_P
APD
APD_P
SEMD1_P
Rev 1
PD0RCV1
PD0RDY#
PD1RCV1
PD1RDY#
SD0RCV1
SD0RDY#
SD1RCV1
SD1RDY#
Bit 0
IDEN0
IDEN0_P
CRSL
CRSL_P
SWAP#
SWAP#_P
SEMD0_P
Rev 0
PD0RCV0
PD0ADV
PD1RCV0
PD1ADV
SD0RCV0
SD0ADV
SD1RCV0
SD1ADV
Default
Value
8Fh
8Fh
FFh
FFh
FFh
FFh
80h
8Ah
00h
00h
00h
00h
00h
00h
00h
00h
- 11 -
Publication Release Date: May 1995
Revision A1

11 Page







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