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PDF GC80303 Data sheet ( Hoja de datos )

Número de pieza GC80303
Descripción I/O Processor
Fabricantes Intel 
Logotipo Intel Logotipo



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Intel® 80303 I/O Processor
Design Guide
April 2002
Order Number: 273308-006

1 page




GC80303 pdf
29 540L PBGA Socket .............................................................................................37
30 JTAG Emulator Connector (Top View)................................................................39
31 Conceptual 3-D View of Processor with a Heat Sink ..........................................45
32 Hole Dimensions for Passive Heatsink ...............................................................46
33 Board Level Keep Out Areas...............................................................................47
34 Clearances of PCI Board and Components ........................................................48
35 Decoupling Schematic.........................................................................................53
36 Primary PCI Interfacel Schematic .......................................................................54
37 Memory Controllerl Schematic ............................................................................55
38 Flash ROM and UARTl Schematic......................................................................56
39 LEDs Schematic..................................................................................................57
40 Logic Analyzer I/Fl Schematic .............................................................................58
41 SDRAM 168-Pin DIMMl Schematic.....................................................................59
42 Secondary PCI/80960 Corel Schematic..............................................................60
43 Secondary PCI Bus 1/2l Schematic ....................................................................61
44 SPCI Pull-Upsl Schematic...................................................................................62
45 Barrtery/Monitorl Schematic ................................................................................63
46 SDRAM +3.3 V Referencel Schematic................................................................64
47 SCKE Control Schematic ....................................................................................65
Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Flash Interface Signals........................................................................................10
ROM, SRAM, or Flash Wait State Profile Programming .....................................11
SDRAM Interface Signals....................................................................................12
Drive Strength Programmability Options .............................................................14
Intel® 80303 I/O Processor Interrupt Routing Signals .........................................24
Memory Controller, Core and JTAG Signals .......................................................29
I2C Bus Signals ...................................................................................................29
PCI Signals..........................................................................................................30
VDIFF Specification for Dual-Power Supply Requirements (3.3 V, 5 V)...............31
Logic Analyzer Header Definitions (Mictor) .........................................................38
Intel® 80303 I/O Processor Debug Connector Wiring .........................................40
Intel® 80303 I/O Processor with PC-1149.1/100F (cable P/N AS01090025-Ax) 41
Intel® 80303 I/O Processor with PCMCIA-1149.1 (cable P/N AS01090025-Bx).42
H-PBGA Package Characteristics.......................................................................44
Heat Sink Vendors and Contacts ........................................................................49
Socket-Header Vendor........................................................................................49
Burn-in Socket Vendor ........................................................................................49
Shipping Tray Vendor..........................................................................................50
JTAG Emulator Vendor .......................................................................................50
Related Documentation.......................................................................................51
Electronic Information..........................................................................................51
IQ80303 Bill of Materials .....................................................................................66
540 L H-PBGA - Ballpad Order ...........................................................................69
Intel® 80303 I/O Processor Design Guide
5

5 Page





GC80303 arduino
Intel® 80303 I/O Processor
Intel® 80303 I/O Processor Memory Subsystem
4.1.1
Figure 3.
Layout Guidelines
Figure 3 illustrates how two Flash devices would interface to the 80303 I/O processor with the
memory controller. The Flash subsystem requires an external latch for address and data
demultiplexing on RAD[16:3]. The data is multiplexed on RAD[16:9].
4 Mbyte Flash Memory System
80960RM/RH
RALE
RAD[16:0]
ROE#
REW#
RCE0#
RCE1#
RAD[2:0]
RAD[8:3]
RAD[16:9]
A[2:0]
A[8:3]
A[22:17]
Latch
A[16:9]
Latch
Intel® 28F016-70
16 Mbit Flash
A[20:0]
OE#
WE#
DQ[7:0]
CE#
Intel® 28F016-70
16 Mbit Flash
A[20:0]
OE#
WE#
DQ[7:0]
CE#
A7655-01
Flash signal loading should not exceed 50 pF. If the system conforms to I2O specification, then a
minimum 16 Mbit Flash such as Intels 28F016SA is suggested.
All traces between the 80303 I/O processor and Flash/SRAM should not exceed 8 inches.
4.1.2
Table 2.
Wait State Profiles
Table 2 summarizes various wait state profiles of SRAM and writable non-volatile memory
devices.
ROM, SRAM, or Flash Wait State Profile Programming
Device Speed
55 ns
115 ns
175 ns
Address-to-Data Wait States
8
12
20
Recovery Wait States
4
4
4
Design Guide
11

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