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PDF 6501 Data sheet ( Hoja de datos )

Número de pieza 6501
Descripción ONE-CHIP MICROCOMPUTER
Fabricantes Commodore 
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MPS
6500/1
ONE-CHIP
MICROCOMPUTER
8500/1 ONE-CHIP MICROCOMPUTER
INTRODucnoN
The MOS Technology 6500/1 Is a complete, high-performance 8-blt NMOS microcomputer on a single chip, and
Is totally upward/downward software compatible with all members of the 6500 family.
The 650011 consists of a 6502 CPU, an Internal clock oscillator, 2048 bytes of Read Only Memory (ROM), 64 bytes
of Random Access Memory (RAM) and flexible Interface circuitry. The· interface circuitry includes a 18-blt
programmable counter/latch with four operating modes, 32 bidirectional Input/output lines (Including two edge-
sensitive lines), five Interrupts and a counter I/O line.
PRODUCT SUPPORT
To allow prototype clrCl~lt development, Mos Tech-
nology offers a PROM compatible 64-pln Emulator de-
vice. This device provides all 650011 Interface lines
plus routing the address bus, data bus, and asso-
ciated control lines off the chip to be connected to
external memory.
Order
Number
ORDERING INFORMATION
Package Frequency Temperature
Type Option
Range
MPS65OOI1
Plastic 1 MHz
MCS6500/1 Ceramic 1 MHz
MPS65OOI1A Plastic 2 MHz
MCS65OOI1A Ceramic 2 MHz
MCS65OOI1E Emulator Device 1MHz
'MCS65OOI1EA Emulator Device 2MHz
O°C to 70°C
O°C to 70°C
O°C to 70°C
O°C to 70°C
Note: The RC frequency option is available only in the
1 MHz 6500/1.
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FEATURES
• 6502 CPU
-Software upward/downward compatibility
-Decimal or binary arithmetic modes
-13 addressing modes
-True direct and indirect indexing
-Memory addressable 110
• 2048 x 8 mask programmable ROM
• 64 x 8 static RAM
• 32 bi<iirectional TIL compatible 110 lines (4 ports)
• 1 bi<iirectional TIL compatible counter I/O line
• 16-bit programmable counter/latch with four
modes
-Interval Timer -Event Counter
-Pulse Generator -Pulse Width Measurement
• Five Interrupts
-Reset
-Non·maskable
-Two external edge sensitive
-Counter
• 1 of 3 frequency references
-Crystal -Clock -RC (resistor only)
• 4 MHz max crystal or clock external frequency
• 2 MHz or 1 MHz internal clock
• 1 /Ls minimum instruction execution
• N-channel, silicon gate, depletion load technology
• Single + 5V power supply
• 500 mW operating power
• Separate power pin for RAM
• 40 pin DIP
• 64 pin PROM compatible Emulator device
Interface Diagram
2-2

1 page




6501 pdf
MPS
6500/1
INSTRUCTION SET -ALPHABETIC SEQUENCE
ADC
AND
ASL
BCC
BCS
BEO
BIT
BMI
BNE
BPL
BRK
BVC
BVS
CLC
CLD
CLI
CLV
CMP
CPX
CPY
DEC
DEX
DEY
EOR
INC
INX
INY
JMP
JSR
Add Memory to Accumulator with Carry
"AND" Memory with Accumulator
Shift Left One Bit (Memory or Accumulator)
Branch on Carry Clear
Branch on Carry Set
Branch on Result Zero
Test Bits in Memory with Accumulator
Branch on Result Minus
Branch on Result not Zero
Branch on Result Plus
Force Break
Branch on Overflow Clear
Branch on Overflow Set
Clear Carry Flag
Clear Decimal Mode
Clear Interrupt Disable Bit
Clear Overflow Flag
Compare Memory and Accumulator
Compare Memory and Index X
Compare Memory and Index Y
Decrement Memory by One
Decrement Index X by One
Decrement Index Y by One
"Exclusive-or" Memory with Accumulator
Increment Memory by One
Increment Index X by One
Increment Index Y by One
Jump to New Location
Jump to New Location Saving Return Address
LOA
LOX
LOY
LSR
NOP
ORA
PHA
PHP
PLA
PLP
ROL
ROR
RTI
RTS
SBC
SEC
SED
SEI
STA
STX
STY
TAX
TAY
TSX
TXA
TXS
TYA
Load Accumulator with Memory
Load Index X with Memory
Load Index Y with Memory
Shift One Bit Right (Memory or Accumulator)
No operation
"OR" Memory with Accumulator
Push Accumulator on Stack
Push Processor Status on Stack
Pull Accumulator from Stack
Pull Processor Status from Stack
Rotate One Bit Left (Memory or Accumulator)
Rotate One Bit Right (Memory or
Accumulator)
Return from Interrupt
Return from Subroutine
Subtract Memory from Accumulator with
Borrow
Set Carry Flag
Set Decimal Mode
Set Interrupt Disable Status
Store Accumulator in Memory
Store Index X in Memory
Store Index Y in Memory
Transfer Accumulator to Index X
Transfer Accumulator to Index Y
Transfer Stack Pointer to Index X
Transfer Index X to Accumulator
Transfer Index X to Stack Register
Transfer Index Y to Accumulator
6500/1 Block Diagram
2-6

5 Page





6501 arduino
MPS
8500/1
PROGRAMMING INSTRUCTIONS FOR MOS TECHNOLOGY 650011
MOS Technology utilizes computer aided techniques to manufacture and test custom bit patterns. New custom
bit data and address Information is supplied on standard 80 column computer cards, 1 Inch wide paper tape, or
standard 1/4 inch wide audio tape cassette, or 270812716 EPROMS. ROM Data will also be accepted In other for·
mats. Consult MOS Technology for details.
MOS TECHNOLOGY (6500) CARD FORMAT
All addresses and related bit patterns must be completely defined. Each deck of cards consists of: 1) Four Title
Cards, 2) Address and Memory Data Records.
Positive logic is generally used on all Input cards: A logic "1" is the most positive or high level (True), and logic
"0" is the most negative or low level (False). This includes chip select specifications as well as bit patterns.
TITLE CARDS
COLUMN
INFORMATION
FIRST CARD
1-4 MOS PART NUMBER (6500/1)
5-80 BLANK (FOR MOS TECHNOLOGY USE)
SECOND CARD
1·20
21·40
41-60
61-80
CUSTOMER NAME
CUSTOMER PART NUMBER
CUSTOMER TECHNICAL CONTACT (PERSON)
CUSTOMER PHONE NUMBER
THIRD CARD
1·20
21·40
41-60
61·80
DATA FORMAT (PUNCH "MOS")
LOGIC FORMAT (PUNCH "POSITIVE" OR "NEGATIVE)
VERIFICATION CODE (PUNCH "HOLD" IF CUSTOMER APPROVAL REO.,
PUNCH "OKAY" IF FINAL APPROVAL NOT REO.)
BLANK (FOR MOS TECHNOLOGY USE)
FOURTH CARD 1-6 PULLUP SELECT CARD (PUNCH "PULLUP")
7 PULLUP OPTION FOR I/O PORT A: 1 PULLUP
8 PULLUP OPTION FOR 110 PORT B;1 = PULLUP
=9 PULLUP OPTION FOR I/O PORT C;1 PULLUP
_ _ _ _10_____ PUL~~~J'21Q~ FOR I/O PORT 0;1 = PULLUP
A set of four (4) Title Cards should accompany each data deck. These cards provide our computer programs ad·
ditional information necessary to accurately produce the ROM Data. These four Title Cards must contain the
above information.
MOS CARD DECK FORMAT
Output data is punched on standard 80 column cards in ASCII Hollerith Code. Each byte of data to be stored is
converted to two half bytes. The half bytes (whose possible values are 0 to FHEX) are translated into their ASCII
equivalents and punched onto cards. Each record contains record length, memory address, and checksum infor·
mation in addition to data. A column by column description of a data record follows.
COLUMN ONE -Record Mark. Signals start of record. ASCII character" ; " (HEX 3B)
COL. 2-3
COL. 4- 7
-Record Length. Two ASCII characters representing a HEX number in the range 0 to 18HEX (0
to 24). This is the count of actual data bytes in the record. A record length of 0 indicates end of
file.
-Load Address. Four ASCII characters. The starting address high and starting address low
are the left and right bytes respectively. The first data byte is stored in the memory location
pOinted to by the load address, succeeding data bytes are loaded into ascending address.
COL. 8-n
-Data. Each 8 bit memory word is represented by two ASCII characters (0 to 9, A to F) to repre·
sent a hexadecimal number (0 to 255).
{
n
=
8
+
2*(RECORD)_
LENGTH
1
}
COL. n + 1- n + 5 -Checksum. The sum of all 8 bit bytes in the record since the record mark ( ; ) in four ASCII
characters (HEX).
REMAINING
COLUMNS
-Not Used. Leave blank or use for comment or labels.
SPECIAL LAST
CARD
-As mentioned above, a record length of zero ("0") indicates an end of file. Following the reo
cord length on this terminal record should be a four character ASCII (HEX) count of all data
records in deck. Following this is the usual checksum for this record.
See the example under heading "MOS PAPER TAPE FORMAT."
A set of four title cards should accompany each data deck.
2-12

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