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PDF MT9VDDT6472H Data sheet ( Hoja de datos )
| Número de pieza | MT9VDDT6472H | |
| Descripción | 512MB DDR SDRAM SODIMM | |
| Fabricantes | Micron | |
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128MB, 256MB, 512MB (x72, ECC, SR) 200-Pin DDR SODIMM
Features
DDR SDRAM SODIMM
MT9VDDT1672H – 128MB1
MT9VDDT3272H – 256MB
MT9VDDT6472H – 512MB
For component data sheets, refer to Micron’s Web site: www.micron.com
Features
• 200-pin, small-outline dual in-line memory module
(SODIMM)
• Fast data transfer rates: PC2100, PC2700, or PC3200
• 128MB (16 Meg x 72), 256MB (32 Meg x 72), and
512MB (64 Meg x 72)
• Supports ECC error detection and correction
• VDD = VDDQ = 2.5V (-40B: VDD = VDDQ = 2.6V)
• VDDSPD = 2.3–3.6V
• 2.5V I/O (SSTL_2-compatible)
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/
received with data—that is, source-synchronous
data capture
• Differential clock inputs (CK and CK#)
• Multiple internal device banks for concurrent
operation
• Selectable burst lengths (BL) 2, 4, or 8
• Auto precharge option
• Auto refresh and self refresh modes: 15.625µs
(128MB) and 7.8125µs (256MB, 512MB) maximum
average periodic refresh interval
• Serial presence-detect (SPD) with EEPROM
• Selectable CAS latency (CL) for maximum
compatibility
• Single rank
• Gold edge contacts
200-Pin SODIMM (MO-224) Figures
Figure 1: Low-Profile Layout
PCB height: 31.75mm (1.25in)
Figure 2: Standard Layout
PCB height: 38.1mm (1.5in)
Options
Marking
• Operating temperature2
– Commercial (0°C TA +70°C)
– Industrial (–40°C TA +85°C)
• Package
None
I
– 200-pin DIMM (standard)
G
– 200-pin DIMM (Pb-free)
Y
• Memory clock, speed, CAS latency
– 5.0ns (200 MHz), 400 MT/s, CL = 3.0
-40B
– 6.0ns (167 MHz), 333 MT/s, CL = 2.5
– 7.5ns (133 MHz), 266 MT/s, CL = 2.03
– 7.5ns (133 MHz), 266 MT/s, CL = 2.03
– 7.5ns (133 MHz), 266 MT/s, CL = 2.53
-335
-262
-26A
-265
Notes: 1. End of life.
2. Contact Micron for industrial temperature
module offerings.
3. Not recommended for new designs.
PDF: 09005aef80804052/Source: 09005aef806e057b
DD9C16_32_64x72H.fm - Rev. F 3/12 EN
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1 page  
128MB, 256MB, 512MB (x72, ECC, SR) 200-Pin DDR SODIMM
Pin Assignments and Descriptions
Table 7: Pin Descriptions
Symbol
A[12:0]
BA[1:0]
CK[2:0], CK#[2:0]
CKE0
DM[8:0]
RAS#, CAS#, WE#
S0#
SA[2:0]
SCL
CB[7:0]
DQ[63:0]
DQS[8:0]
SDA
VDD
VDDSPD
VREF
VSS
NC
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
I/O
I/O
I/O
Supply
Supply
Supply
Supply
–
Description
Address inputs: Provide the row address for ACTIVE commands, and the
column address and auto precharge bit (A10) for READ/WRITE commands, to
select one location out of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines whether the PRECHARGE
applies to one device bank (A10 LOW, device bank selected by BA[1:0]) or all
device banks (A10 HIGH). The address inputs also provide the op-code during a
MODE REGISTER SET command. BA[1:0] define which mode register (or
extended mode register) is loaded during the LOAD MODE REGISTER
command. A[11:0] (128MB) and A[12:0] (256MB, 512MB).
Bank address: BA[1:0] define the device bank to which an ACTIVE, READ,
WRITE, or PRECHARGE command is being applied.
Clock: CK and CK# are differential clock inputs. All control, command, and
address input signals are sampled on the crossing of the positive edge of CK
and the negative edge of CK#. Output data (DQ and DQS) is referenced to the
crossings of CK and CK#.
Clock enable: CKE enables (registered HIGH) and disables (registered LOW)
the internal clock, input buffers, and output drivers.
Input data mask: DM is an input mask signal for write data. Input data is
masked when DM is sampled HIGH, along with that input data, during a write
access. DM is sampled on both edges of DQS. Although DM pins are input-only,
the DM loading is designed to match that of the DQ and DQS pins.
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command
being entered.
Chip selects: S# enables (registered LOW) and disables (registered HIGH) the
command decoder.
Presence-detect address inputs: These pins are used to configure the
presence-detect device.
Serial clock for presence-detect: SCL is used to synchronize the presence-
detect data transfer to and from the module.
Check bits.
Data input/output: Data bus.
Data strobe: Output with read data. Edge-aligned with read data. Input with
write data. Center-aligned with write data. Used to capture data.
Serial presence-detect data: SDA is a bidirectional pin used to transfer
addresses and data into and out of the presence-detect portion of the module.
Power supply: 2.5V ±0.2V (-40B: 2.6V ±0.1V).
Serial EEPROM positive power supply: 2.3–3.6V.
SSTL_2 reference voltage (VDD/2).
Ground.
No connect: These pins are not connected on the module.
PDF: 09005aef80804052/Source: 09005aef806e057b
DD9C16_32_64x72H.fm - Rev. F 3/12 EN
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved
5 Page 
128MB, 256MB, 512MB (x72, ECC, SR) 200-Pin DDR SODIMM
Electrical Specifications
Table 11:
IDD Specifications and Conditions – 256MB (Die Revision F)
Values are shown for the MT46V32M8 DDR SDRAM only and are computed from values specified in the
256Mb (32 Meg x 8) component data sheet
Parameter/Condition
Operating one bank active-precharge current:
tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs
changing once per clock cycle; Address and control inputs
changing once every two clock cycles
Operating one bank active-read-precharge current:
BL = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address
and control inputs changing once per clock cycle
Precharge power-down standby current: All device banks
idle; Power-down mode; tCK = tCK (MIN); CKE = LOW
Idle standby current: CS# = HIGH; All device banks idle;
tCK = tCK (MIN); CKE = HIGH; Address and other control
inputs changing once per clock cycle; VIN = VREF for DQ, DM,
and DQS
Active power-down standby current: One device bank
active; Power-down mode; tCK = tCK (MIN); CKE = LOW
Active standby current: CS# = HIGH; CKE = HIGH; One
device bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ,
DM, and DQS inputs changing twice per clock cycle; Address
and other control inputs changing once per clock cycle
Operating burst read current: BL = 2; Continuous burst
reads; One device bank active; Address and control inputs
changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA
Operating burst write current: BL = 2; Continuous burst
writes; One device bank active; Address and control inputs
changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and
DQS inputs changing twice per clock cycle
Auto refresh current
tREFC = tRFC
(MIN)
tREFC = 7.8125µs
Self refresh current: CKE 0.2V
Operating bank interleave read current: Four device bank
interleaving reads (BL = 4) with auto precharge;
tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs
change only during active READ or WRITE commands
Symbol
IDD0
IDD1
IDD2P
IDD2F
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD5A
IDD6
IDD7
-40B
1215
1530
36
540
360
630
1800
1755
2340
54
36
4230
-335
1125
1530
36
450
270
540
1575
1575
2295
54
36
3690
-262
1125
1440
36
405
225
450
1350
1350
2115
54
36
3150
-265
1080
Units
mA
1305
mA
36 mA
405 mA
270 mA
450 mA
1350
mA
1350
mA
2205
54
36
3285
mA
mA
mA
PDF: 09005aef80804052/Source: 09005aef806e057b
DD9C16_32_64x72H.fm - Rev. F 3/12 EN
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet MT9VDDT6472H.PDF ] | |
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