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PDF MT9HVF12872PK Data sheet ( Hoja de datos )

Número de pieza MT9HVF12872PK
Descripción 1GB DDR2 SDRAM VLP Mini-RDIMM
Fabricantes Micron 
Logotipo Micron Logotipo



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512MB, 1GB: (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM
Features
DDR2 SDRAM VLP Mini-RDIMM
MT9HVF6472(P)K – 512MB
MT9HVF12872(P)K – 1GB
For component data sheets, refer to Micron’s Web site: www.micron.com
Features
• 244-pin, very low profile mini registered dual in-line
memory module (VLP Mini-RDIMM)
• Fast data transfer rates: PC2-3200, PC2-4200,
PC2-5300, or PC2-6400
• 512MB (64 Meg x 72) or 1GB (128 Meg x 72)
• Supports ECC error detection and correction
• VDD = VDDQ = +1.8V
• VDDSPD = +1.7V to +3.6V
• JEDEC-standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
• 4n-bit prefetch architecture
• Multiple internal device banks for concurrent
operation
• Supports duplicate output strobe (RDQS/RDQS#)
• Programmable CAS# latency (CL)
• Posted CAS# additive latency (AL)
• WRITE latency = READ latency - 1 tCK
• Programmable burst lengths: 4 or 8
• Adjustable data-output drive strength
• 64ms, 8,192-cycle refresh
• On-die termination (ODT)
• Serial presence-detect (SPD) with EEPROM
• Gold edge contacts
• Single rank
Figure 1: 244-Pin VLP Mini-RDIMM
PCB height: 18.2mm (0.72in)
Options
• Parity
• Operating temperature1
Commercial (0°C TA +70°C)
Industrial (–40°C TA +85°C)
• Package
244-pin DIMM (Pb-free)
• Frequency/CAS latency2
2.5ns @ CL = 5 (DDR2-800)
2.5ns @ CL = 6 (DDR2-800)
3ns @ CL = 5 (DDR2-667)
3.75ns @ CL = 4 (DDR2-533)
5.0ns @ CL = 3 (DDR2-400)
• PCB height
18.2mm (0.72in)
Marking
P
None
I
Y
-80E
-800
-667
-53E
-40E
Notes: 1. Contact Micron for industrial temperature
module offerings.
2. CL = CAS (READ) latency; registered mode
will add one clock cycle to CL.
Table 1:
Speed
Grade
-80E
-800
-667
-53E
-40E
Key Timing Parameters
Industry
Nomenclature
PC2-6400
PC2-6400
PC2-5300
PC2-4200
PC2-3200
CL = 6
800
Data Rate (MT/s)
CL = 5
800
667
667
CL = 4
533
53E
533
533
400
CL = 3
400
400
400
tRCD
(ns)
12.5
15
15
15
15
tRP
(ns)
tRC
(ns)
12.5 55
15 55
15 55
15 55
15 55
PDF: 09005aef81c9620b/Source: 09005aef81c961ec
HVF9C64_128x72K.fm - Rev. C 3/07 EN
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.

1 page




MT9HVF12872PK pdf
512MB, 1GB: (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM
Pin Assignments and Descriptions
Table 6: Pin Descriptions (continued)
Symbol
VREF
VSS
VDDSPD
NC
RFU
Type
Supply
Supply
Supply
Description
SSTL_18 reference voltage.
Ground.
Serial EEPROM positive power supply: +1.7V to +3.6V.
No connect: These pins should be left unconnected.
Reserved for future use.
PDF: 09005aef81c9620b/Source: 09005aef81c961ec
HVF9C64_128x72K.fm - Rev. C 3/07 EN
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.

5 Page





MT9HVF12872PK arduino
512MB, 1GB: (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM
Register and PLL Specifications
Register and PLL Specifications
Table 11: Register Specifications
SSTU32865 device or equivalent JESD82-19
Parameter
DC high-level
input voltage
DC low-level
input voltage
AC high-level
input voltage
AC low-level
input voltage
Output high voltage
Output low voltage
Input current
Static standby
Static operating
Dynamic operating
(clock tree)
Dynamic operating
(per each input)
Input capacitance
(per device, per pin)
Input capacitance
(per device, per pin)
Symbol
Pins
Condition
VIH(DC)
VIL(DC)
VIH(AC)
VIL(AC)
VOH
VOL
II
IDD
IDD
IDDD
IDDD
CI
CI
Address,
control,
command
SSTL_18
Address,
control,
command
SSTL_18
Address,
control,
command
SSTL_18
Address,
control,
command
SSTL_18
Parity output
LVCMOS
Parity output
LVCMOS
All pins
VI = VDDQ or VSSQ
All pins
RESET# = VSSQ (IO = 0)
All pins
RESET# = VSSQ;
VI = VIH(AC) or VIL(DC)
IO = 0
n/a RESET# = VDD, VI = VIH(AC) or
VIL(AC), IO = 0; CK and CK#
switching 50% duty cycle
n/a RESET# = VDD, VI = VIH(AC) or
VIL(AC), IO = 0; CK and CK#
switching 50% duty cycle;
One data input switching at
tCK/2, 50% duty cycle
All inputs
except RESET#
VI = VREF ±250mV;
VDDQ = 1.8V
RESET#
VI = VDDQ or VSSQ
Min
VREF(DC) + 125
0
VREF(DC) + 250
0
1.2
–5
2.5
Max
Units
VDDQ + 250 mV
VREF(DC) - 125 mV
VDD
mV
VREF(DC) - 250 mV
–V
0.5 V
+5 µA
200 µA
80 mA
Varies by
µA
manufacturer
Varies by
µA
manufacturer
3.5 pF
Varies by
pF
manufacturer
Notes:
1. Timing and switching specifications for the register listed above are critical for proper oper-
ation of the DDR2 SDRAM registered DIMMs. These are meant to be a subset of the param-
eters for the specific device used on the module. Detailed information for this register is
available in JEDEC standard JESD82.
PDF: 09005aef81c9620b/Source: 09005aef81c961ec
HVF9C64_128x72K.fm - Rev. C 3/07 EN
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.

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