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PDF MT8HTF3264AY Data sheet ( Hoja de datos )
| Número de pieza | MT8HTF3264AY | |
| Descripción | 256MB DDR2 SDRAM UDIMM | |
| Fabricantes | Micron | |
| Logotipo |  |
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256MB, 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Features
DDR2 SDRAM UDIMM
MT8HTF3264AY – 256MB
MT8HTF6464AY – 512MB
MT8HTF12864AY – 1GB
Features
• 240-pin, unbuffered dual in-line memory module
• Fast data transfer rates: PC2-3200, PC2-4200,
PC2-5300, PC2-6400, or PC2-8500
• 256MB (32 Meg x 64), 512MB (64 Meg x 64),
or 1GB (128 Meg x 64
• VDD = VDDQ = 1.8V
• VDDSPD = 1.7–3.6V
• JEDEC-standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
• 4n-bit prefetch architecture
• Multiple internal device banks for concurrent
operation
• Programmable CAS latency (CL)
• Posted CAS additive latency (AL)
• WRITE latency = READ latency - 1 tCK
• Programmable burst lengths (BL): 4 or 8
• Adjustable data-output drive strength
• 64ms, 8192-cycle refresh
• On-die termination (ODT)
• Serial presence detect (SPD) with EEPROM
• Gold edge contacts
• Single rank
Figure 1: 240-Pin UDIMM (MO-237 R/C A and D)
PCB height: 30.0mm (1.18in)
Options
• Operating temperature
– Commercial (0°C ≤ TA ≤ +70°C)
– Industrial (–40°C ≤ TA ≤ +85°C)1
• Package
– 240-pin DIMM (lead-free)
• Frequency/CL2
– 1.875ns @ CL = 7 (DDR2-1066)3
– 2.5ns @ CL = 5 (DDR2-800)
– 2.5ns @ CL = 6 (DDR2-800)
– 3.0ns @ CL = 5 (DDR2-667)
– 3.75ns @ CL = 4 (DDR2-533)4
– 5.0ns @ CL = 3 (DDR2-400)
Marking
None
I
Y
-1GA
-80E
-800
-667
-53E
-40E
Notes:
1. Contact Micron for industrial temperature
module offerings.
2. CL = CAS (READ) latency.
3. Available only in 1GB, Rev. E devices.
4. Not recommended for new designs.
Table 1: Key Timing Parameters
Speed
Grade
-1GA
-80E
-800
-667
-53E
-40E
Industry
Nomenclature
PC2-8500
PC2-6400
PC2-6400
PC2-5300
PC2-4200
PC2-3200
CL = 7
1066
Data Rate (MT/s)
CL = 6 CL = 5 CL = 4
800 667 533
800 800 533
800 667 533
– 667 553
– – 553
– – 400
CL = 3
400
400
400
400
400
400
tRCD
(ns)
13.125
12.5
15
15
15
15
tRP
(ns)
13.125
12.5
15
15
15
15
tRC
(ns)
58.125
57.5
60
60
55
55
PDF: 09005aef80e2ff8d
htf8c32_64_128x64aypdf - Rev. G 3/10 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2003 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1 page  
256MB, 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Pin Descriptions
Pin Descriptions
The pin description table below is a comprehensive list of all possible pins for all DDR2
modules. All pins listed may not be supported on this module. See Pin Assignments for
information specific to this module.
Table 7: Pin Descriptions
Symbol
Ax
Type
Input
BAx
CKx,
CK#x
CKEx
DMx,
Input
Input
Input
Input
ODTx
Input
Par_In
RAS#, CAS#, WE#
RESET#
S#x
SAx
SCL
CBx
DQx
DQSx,
DQS#x
Input
Input
Input
Input
Input
Input
I/O
I/O
I/O
Description
Address inputs: Provide the row address for ACTIVE commands, and the column ad-
dress and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code
during a LOAD MODE command. See the Pin Assignments Table for density-specific
addressing information.
Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA define which mode register (MR0, MR1,
MR2, and MR3) is loaded during the LOAD MODE command.
Clock: Differential clock inputs. All control, command, and address input signals are
sampled on the crossing of the positive edge of CK and the negative edge of CK#.
Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circui-
try and clocks on the DDR2 SDRAM.
Data mask (x8 devices only): DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH, along with that input data, during a write ac-
cess. Although DM pins are input-only, DM loading is designed to match that of the
DQ and DQS pins.
On-die termination: Enables (registered HIGH) and disables (registered LOW) termi-
nation resistance internal to the DDR2 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input
will be ignored if disabled via the LOAD MODE command.
Parity input: Parity bit for Ax, RAS#, CAS#, and WE#.
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Reset: Asynchronously forces all registered outputs LOW when RESET# is LOW. This
signal can be used during power-up to ensure that CKE is LOW and DQ are High-Z.
Chip select: Enables (registered LOW) and disables (registered HIGH) the command
decoder.
Serial address inputs: Used to configure the SPD EEPROM address range on the I2C
bus.
Serial clock for SPD EEPROM: Used to synchronize communication to and from the
SPD EEPROM on the I2C bus.
Check bits. Used for system error detection and correction.
Data input/output: Bidirectional data bus.
Data strobe: Travels with the DQ and is used to capture DQ at the DRAM or the con-
troller. Output with read data; input with write data for source synchronous opera-
tion. DQS# is only used when differential data strobe mode is enabled via the LOAD
MODE command.
PDF: 09005aef80e2ff8d
htf8c32_64_128x64aypdf - Rev. G 3/10 EN
5 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2003 Micron Technology, Inc. All rights reserved.
5 Page 
256MB, 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
DRAM Operating Conditions
DRAM Operating Conditions
Recommended AC operating conditions are given in the DDR2 component data sheets.
Component specifications are available on Micron's Web site. Module speed grades cor-
relate with component speed grades.
Table 9: Module and Component Speed Grades
DDR2 components may exceed the listed module speed grades; module may not be available in all listed speed grades
Module Speed Grade
Component Speed Grade
-1GA
-187E
-80E
-25E
-800
-25
-667
-3
-53E
-37E
-40E
-5E
Design Considerations
Simulations
Micron memory modules are designed to optimize signal integrity through carefully de-
signed terminations, controlled board impedances, routing topologies, trace length
matching, and decoupling. However, good signal integrity starts at the system level. Mi-
cron encourages designers to simulate the signal characteristics of the system's memo-
ry bus to ensure adequate signal integrity of the entire memory system.
Power
Operating voltages are specified at the DRAM, not at the edge connector of the module.
Designers must account for any system voltage drops at anticipated power levels to en-
sure the required supply voltage is maintained.
PDF: 09005aef80e2ff8d
htf8c32_64_128x64aypdf - Rev. G 3/10 EN
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2003 Micron Technology, Inc. All rights reserved.
11 Page | ||
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