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PDF MT36LSDT25672 Data sheet ( Hoja de datos )

Número de pieza MT36LSDT25672
Descripción 2GB Synchronous DRAM Module
Fabricantes Micron 
Logotipo Micron Logotipo



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No Preview Available ! MT36LSDT25672 Hoja de datos, Descripción, Manual

1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Features
Synchronous DRAM Module
MT36LSDT12872 – 1GB
MT36LSDT25672 – 2GB
For the latest data sheet, refer to Micron’s Web site: www.micron.com/products/modules
Features
• 168-pin, dual in-line memory module (DIMM)
• PC100- and PC133-compliant
• Registered inputs with one-clock delay
• Phase-lock loop (PLL) clock driver to reduce loading
• Utilizes 125 MHz and 133 MHz SDRAM
components
• Supports ECC error detection and correction
• 1GB (128 Meg x 72) and 2GB (256 Meg x 72)
• Single +3.3V power supply
• Fully synchronous; all signals registered on positive
edge of PLL clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal SDRAM banks for hiding row access/
precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto precharge
• Auto refresh mode
• Self refresh mode: 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Serial presence-detect (SPD)
• Gold edge contacts
Table 1:
Timing Parameters
CL = CAS (READ) latency
Module
Marking
-13E
-133
Clock
133 MHz
133 MHz
Access Time
CL = 2
5.4ns
CL = 3
5.4ns
Setup
Time
1.5
1.5
Hold
Time
0.8
0.8
Figure 1: 168-Pin DIMM (MO-161)
Standard 1.70in. (43.18mm)
Low-Profile 1.20in. (30.48mm)
Options
• Package
168-pin DIMM (standard)
168-pin DIMM (lead-free)
• Frequency/CAS Latency2
133 MHz/CL = 2
133 MHz/CL = 3
• PCB
Standard 1.70in (43.18mm)
Low-Profile 1.20in. (30.48mm)
Marking
G
Y1
-13E
-133
See note on page 2
See note on page 2
Notes: 1. Contact Micron for product availability.
2. Registered mode adds one clock cycle to CL.
Table 2: Address Table
Parameter
Refresh Count
Device Banks
Device Configuration
Row Addressing
Column Addressing
Module Ranks
1GB
8K
4 (BA0, BA1)
256Mb (64 Meg x 4)
8K (A0–A12)
2K (A0–A9, A11)
2 (S0#, S2#; S1#, S3#)
2GB
8K
4 (BA0, BA1)
512Mb (128 Meg x 4)
8K (A0–A12)
4K (A0–A9, A11, A12)
2 (S0#, S2#; S1#, S3#)
PDF: 09005aef80b1835d/Source: 09005aef80b18348
SD36C128_256x72G.fm - Rev. E 6/05 EN
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.

1 page




MT36LSDT25672 pdf
1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Functional Block Diagram
Table 5:
Pin Descriptions (Continued)
Pin numbers may not correlate with symbol order; refer to Table 4 on page 3 for more information
Pin Numbers
6, 18, 26, 40, 41, 49, 59, 73, 84,
90, 102, 110, 124, 133, 143,
157, 168
1, 12, 23, 32, 43, 54, 64, 68, 78,
85, 96, 107, 116, 127, 138, 148,
152, 162
24, 25, 31, 44, 48 50, 51 61, 62,
63, 80, 81, 108, 109, 132, 134,
135, 145, 146, 164
Symbol
VDD
VSS
NC
Type
Description
Supply Power supply: +3.3V ±0.3V.
Supply Ground.
– Not connected: Listed pins are not connected on these
modules.
Functional Block Diagram
All resistor values are 10Ω unless otherwise specified.
‘t’ indicates top portion of stacked SDRAM. ‘b’ indicates bottom portion of stacked
SDRAM.
Per industry standard, Micron modules utilize various component speed grades, as ref-
erenced in the module part number guide at www.micron.com/support/number-
ing.html.
Standard modules use the following SDRAM devices: MT48LC64M4A2TG (1GB);
MT48LC128M4A2TG (2GB). Lead-free modules use the following SDRAM devices:
MT48LC64M4A2P (1GB); MT48LC128M4A2P (2GB).
PDF: 09005aef80b1835d/Source: 09005aef80b18348
SD36C128_256x72G.fm - Rev. E 6/05 EN
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.

5 Page





MT36LSDT25672 arduino
1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Mode Register Definition
Figure 5: CAS Latency Diagram
T0 T1 T2 T3
CLK
COMMAND
DQ
READ
NOP
tLZ
tAC
CAS latency = 2
NOP
tOH
DOUT
Burst Type
CAS Latency
CLK
COMMAND
T0
READ
DQ
T1 T2
NOP NOP
tLZ
tAC
CAS latency = 3
T3 T4
NOP
tOH
DOUT
DON’T CARE
UNDEFINED
Accesses within a given burst may be programmed to be either sequential or interleaved;
this is referred to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst type
and the starting column address, as shown in Table 6 on page 10.
The CAS latency is the delay, in clock cycles, between the registration of a READ com-
mand and the availability of the first piece of output data. The latency can be set to two
or three clocks.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available by clock edge n + m. The DQ will start driving as a result of the clock
edge one cycle earlier (n + m - 1), and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example, assuming that the clock cycle
time is such that all relevant access times are met, if a read command is registered at T0
and the latency is programmed to two clocks, the DQ will start driving after T1 and the
data will be valid by T2, as shown in the Figure 5 on page 11. Table 7 on page 12, indi-
cates the operating frequencies at which each CAS latency setting can be used.
Reserved states should not be used as unknown operation or incompatibility with future
versions may result.
PDF: 09005aef80b1835d/Source: 09005aef80b18348
SD36C128_256x72G.fm - Rev. E 6/05 EN
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.

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