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PDF MT18HTF12872 Data sheet ( Hoja de datos )

Número de pieza MT18HTF12872
Descripción 1GB DDR2 SDRAM Registered DIMM
Fabricantes Micron 
Logotipo Micron Logotipo



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No Preview Available ! MT18HTF12872 Hoja de datos, Descripción, Manual

512MB, 1GB, 2GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
Features
DDR2 SDRAM Registered DIMM (RDIMM)
MT18HTF6472 – 512MB
MT18HTF12872(P) – 1GB
MT18HTF25672(P) – 2GB
For component data sheets, refer to Micron's Web site: www.micron.com
Features
• 240-pin, registered dual in-line memory module
• Fast data transfer rates: PC2-3200, PC2-4200, PC2-
5300, or PC2-6400
• Supports ECC error detection and correction
• VDD = VDDQ = +1.8V
• VDDSPD = +1.7V to +3.6V
• JEDEC-standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
• 4n-bit prefetch architecture
• Single rank
• Multiple internal device banks for concurrent
operation
• Programmable CAS# latency (CL)
• Posted CAS# additive latency (AL)
• WRITE latency = READ latency - 1 tCK
• Programmable burst lengths: 4 or 8
• Adjustable data-output drive strength
• 64ms, 8,192-cycle refresh
• On-die termination (ODT)
• Serial presence-detect (SPD) with EEPROM
• Gold edge contacts
Figure 1:
240-Pin RDIMM (MO-237
R/C C–Non-Parity, R/C H–Parity)
PCB height: 30mm (1.18in)
Options
• Parity3
• Operating temperature1
Commercial (0°C TA +70°C)
Industrial (–40°C TA +85°C)
• Package
240-pin DIMM (Pb-free)
• Frequency/CAS latency2
2.5ns @CL = 5 (DDR2-800)3
2.5ns @ CL = 6 (DDR2-800)3
3.0ns @ CL = 5 (DDR2-667)3
3.75ns @ CL = 4 (DDR2-533)
5.0ns @ CL = 3 (DDR2-400)
• PCB height
30mm (1.18in)
Marking
P
None
I
Y
-80E
-800
-667
-53E
-40E
Notes: 1. Contact Micron for industrial temperature
module offerings.
2. CL = CAS (READ) latency; registered mode
will add one clock cycle to CL.
3. Not available in 512MB density.
Table 1: Key Timing Parameters
Speed
Grade
-80E
-800
-667
-53E
-40E
Industry
Nomenclature
PC2-6400
PC2-6400
PC2-5300
PC2-4200
PC2-3200
CL = 6
800
Data Rate (MT/s)
CL = 5
800
667
667
CL = 4
533
533
533
533
400
CL = 3
400
400
400
tRCD
(ns)
12.5
15
15
15
15
tRP
(ns)
tRC
(ns)
12.5 55
15 55
15 55
15 55
15 55
PDF: 09005aef80e5e752/Source: 09005aef80e5e626
HTF18C64_128_256x72.fm - Rev. E 3/07 EN
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.

1 page




MT18HTF12872 pdf
512MB, 1GB, 2GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
Functional Block Diagram
Functional Block Diagram
Figure 2: Functional Block Diagram
PAR_IN
S0#
BA0–BA1/BA2
A0–A12/A13
RAS#
CAS#
WE#
CKE0
ODT0
RESET#
VSS
RS0#
DQS0
DQS0#
DQ0
DQ1
DQ2
DQ3
DQS1
DQS1#
DQ8
DQ9
DQ10
DQ11
DQS2
DQS2#
DQ16
DQ17
DQ18
DQ19
DQS3
DQS3#
DQ24
DQ25
DQ26
DQ27
DQS4
DQS4#
DQ32
DQ33
DQ34
DQ35
DQS5
DQS5#
DQ40
DQ41
DQ42
DQ43
DQS6
DQS6#
DQ48
DQ49
DQ50
DQ51
DQS7
DQS7#
DQ56
DQ57
DQ58
DQ59
DQS8
DQS8#
CB0
CB1
CB2
CB3
DM CS# DQS DQS#
DQ
DQ U1
DQ
DQ
DM CS# DQS DQS#
DQ
DQ U2
DQ
DQ
DM CS# DQS DQS#
DQ
DQ U3
DQ
DQ
DM CS# DQS DQS#
DQ
DQ U4
DQ
DQ
DM CS# DQS DQS#
DQ
DQ U9
DQ
DQ
DM CS# DQS DQS#
DQ
DQ U10
DQ
DQ
DM CS# DQS DQS#
DQ
DQ U11
DQ
DQ
DM CS# DQS DQS#
DQ
DQ U12
DQ
DQ
DM CS# DQS DQS#
DQ
DQ U5
DQ
DQ
U6, U17
R
e
g
i
s
t
e
r
ERR_OUT
RS0#: DDR2 SDRAM
RBA0RBA1/RBA2: DDR2 SDRAM
RA0–RA12/RA13: DDR2 SDRAM
RRAS#: DDR2 SDRAM
RCAS#: DDR2 SDRAM
RWE#: DDR2 SDRAM
VDDSPD
RCKE0: DDR2 SDRAM
RODT0: DDR2 SDRAM
VDD/VDDQ
VREF
VSS
DQS9
DQS9#
DQ4
DQ5
DQ6
DQ7
DQS10
DQS10#
DQ12
DQ13
DQ14
DQ15
DQS11
DQS11#
DQ20
DQ21
DQ22
DQ23
DQS12
DQS12#
DQ28
DQ29
DQ30
DQ31
DQS13
DQS13#
DQ36
DQ37
DQ38
DQ39
DQS14
DQS14#
DQ44
DQ45
DQ46
DQ47
DQS15
DQS15#
DQ52
DQ53
DQ54
DQ55
DQS16
DQS16#
DQ60
DQ61
DQ62
DQ63
DQS17
DQS17#
CB4
CB5
CB6
CB7
DM CS# DQS DQS#
DQ
DQ U22
DQ
DQ
DM CS# DQS DQS#
DQ
DQ U21
DQ
DQ
DM CS# DQS DQS#
DQ
DQ U20
DQ
DQ
DM CS# DQS DQS#
DQ
DQ U19
DQ
DQ
DM CS# DQS DQS#
DQ
DQ U16
DQ
DQ
DM CS# DQS DQS#
DQ
DQ U15
DQ
DQ
DM CS# DQS DQS#
DQ
DQ U14
DQ
DQ
DM CS# DQS DQS#
DQ
DQ U13
DQ
DQ
DM CS# DQS DQS#
DQ
DQ U18
DQ
DQ
U8
CK0
CK0#
SPD EEPROM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
SCL
PLL
RESET#
U7
SPD EEPROM
WP A0 A1 A2
VSS SA0 SA1 SA2
SDA
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
Register x 2
PDF: 09005aef80e5e752/Source: 09005aef80e5e626
HTF18C64_128_256x72.fm - Rev. E 3/07 EN
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.

5 Page





MT18HTF12872 arduino
512MB, 1GB, 2GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
IDD Specifications
Table 13:
DDR2 IDD Specifications and Conditions (Die Revision E) – 2GB
Values shown for MT47H256M4 DDR2 SDRAM only and are computed from values specified in the
1Gb (256 Meg x 4) component data sheet
Parameter/Condition
Operating one bank active-precharge current: tCK = tCK (IDD),
tRC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between
valid commands; Address bus inputs are switching; Data bus inputs are
switching
Operating one bank active-read-precharge current: IOUT = 0mA;
BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS
MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data pattern is same as
IDD4W
Precharge power-down current: All device banks idle; tCK = tCK (IDD);
CKE is LOW; Other control and address bus inputs are stable; Data bus
inputs are floating
Precharge quiet standby current: All device banks idle; tCK = tCK (IDD);
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching;
Data bus inputs are switching
Active power-down current: All device banks open;
Fast PDN exit
tCK = tCK (IDD); CKE is LOW; Other control and address bus MR[12] = 0
inputs are stable; Data bus inputs are floating
Slow PDN exit
MR[12] = 1
Active standby current: All device banks open; tCK = tCK (IDD),
tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between
valid commands; Other control and address bus inputs are switching;
Data bus inputs are switching
Operating burst write current: All device banks open; Continuous
burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD),
tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between
valid commands; Address bus inputs are switching; Data bus inputs are
switching
Operating burst read current: All device banks open; Continuous burst
reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD),
tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between
valid commands; Address bus inputs are switching; Data bus inputs are
switching
Burst refresh current: tCK = tCK (IDD); REFRESH command at every
tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands;
Other control and address bus inputs are switching; Data bus inputs are
switching
Self refresh current: CK and CK# at 0V; CKE 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving
reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 x tCK (IDD);
tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is
HIGH, S# is HIGH between valid commands; Address bus inputs are stable
during deselects; Data bus inputs are switching
Symbol
IDD0
IDD1
IDD2P
IDD2Q
IDD2N
IDD3P
IDD3N
IDD4W
IDD4R
IDD5
IDD6
IDD7
-80E/
-800
1,620
1,980
126
900
900
720
180
1,080
2,880
2,880
4,230
126
6,030
-667 -53E -40E Units
1,530 1,260 1,260 mA
1,800 1,710 1,620 mA
126 126 126 mA
720 720 630 mA
720 720 630 mA
540 540 540 mA
180 180 180 mA
990 810 720 mA
2,430 2,250 1,890 mA
2,430 2,250 1,890 mA
3,870 3,780 3,690 mA
126 126 126 mA
5,040 4,860 4,680 mA
PDF: 09005aef80e5e752/Source: 09005aef80e5e626
HTF18C64_128_256x72.fm - Rev. E 3/07 EN
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.

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