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PDF MT16VDDT25664A Data sheet ( Hoja de datos )

Número de pieza MT16VDDT25664A
Descripción 2GB DDR SDRAM UNBUFFERED DIMM
Fabricantes Micron 
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256MB, 512MB, 1GB, 2GB (x64, DR)
184-PIN DDR SDRAM UDIMM
DDR SDRAM
UNBUFFERED DIMM
MT16VDDT3264A – 256MB
MT16VDDT6464A – 512MB
MT16VDDT12864A
MT16VDDT25664A
1GB
2GB
(ADVANCE)
For the latest data sheet, please refer to the MicronWeb
site: www.micron.com/products/modules
Features
• 184-pin, dual in-line memory module (DIMM)
• Fast data transfer rates: PC2100 or PC2700
• Utilizes 266 MT/s and 333 MT/s DDR SDRAM
components
• 256MB (32 Meg x 64), 512MB (64 Meg x 64), 1GB
(128 Meg x 64), and 2GB (256 Meg x 64)
• VDD = VDDQ = +2.5V
• VDDSPD = +2.3V to +3.6V
• 2.5V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/
received with data—i.e., source-synchronous data
capture
• Differential clock inputs (CK and CK#)
• Four internal device banks for concurrent operation
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• 15.6µs (256MB), 7.8125µs (512MB, 1GB, and 2GB)
maximum average periodic refresh interval
• Serial Presence Detect (SPD) with EEPROM
• Programmable READ CAS latency
• Gold edge contacts
Figure 1: 184-Pin DIMM (MO-206)
Standard 1.25in. (31.75mm)
Low-Profile 1.15in. (29.21mm)
OPTIONS
MARKING
• Package
184-pin DIMM (standard)
G
184-pin DIMM (lead-free)1
• Memory Clock, Speed, CAS Latency2
Y
6ns/166MHz (333 MT/s) CL = 2.5
7.5ns/133 MHz (266 MT/s) CL = 2
7.5ns/133 MHz (266 MT/s) CL = 2
-335
-2621
-26A1
7.5ns/133 MHz (266 MT/s) CL = 2.5
-265
• PCB
Standard 1.25in. (31.75mm)
See page 2 note
Low-Profile 1.20in. (30.48mm)
See page 2 note
NOTE: 1. Consult Micron for product availability.
2. CL = CAS (READ) Latency.
Table 1: Address Table
Refresh Count
Row Addressing
Device Bank Addressing
Device Configuration
Column Addressing
Module Rank Addressing
256MB
4K
4K (A0–A11)
4 (BA0, BA1)
128Mb (16 Meg x 8)
1K (A0–A9)
2 (S0#, S1#)
512MB
8K
8K (A0–A12)
4 (BA0, BA1)
256Mb (32 Meg x 8)
1K (A0–A9)
2 (S0#, S1#)
1GB
8K
8K (A0–A12)
4 (BA0, BA1)
512Mb (64 Meg x 8)
2K (A0–A9, A11)
2 (S0#, S1#)
2GB
8K
16K (A0–A13)
4 (BA0, BA1)
1Gb (128 Meg x 8)
2K (A0–A9, A11)
2 (S0#, S1#)
pdf: 09005aef80739fa5, source: 09005aef807397e5
DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN
1
©2004 Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.

1 page




MT16VDDT25664A pdf
256MB, 512MB, 1GB, 2GB (x64, DR)
184-PIN DDR SDRAM UDIMM
Table 5: Pin Descriptions (Continued)
Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information
PIN NUMBERS
2, 4, 6, 8, 12, 13, 19, 20, 23,
24, 28, 31, 33, 35, 39, 40, 53,
55, 57, 60, 61, 64, 68, 69, 72,
73, 79, 80, 83, 84, 87, 88, 94,
95, 98, 99, 105, 106, 109, 110,
114, 117, 121, 123, 126, 127,
131, 133, 146, 147, 150, 151,
153, 155, 161, 162, 165, 166,
170, 171, 174, 175, 178, 179
92
181,182, 183
91
1
15, 22, 30, 54, 62, 77, 96, 104,
112, 128, 136, 143, 156, 164,
172, 180
7, 38, 46, 70, 85, 108, 120,
148, 168
3, 11, 18, 26, 34, 42, 50, 58,
66, 74, 81, 89, 93, 100, 116,
124, 132, 139, 145, 152, 160,
176
184
44, 45, 47, 49, 51, 134, 135,
140, 142, 144
9, 10, 71, 82, 90, 101, 102,
103, 113, 115 (256MB), 163,
167 (256MB, 512MB, 1GB),
173
SYMBOL
DQ0–DQ63
SCL
SA0–SA2
SDA
VREF
VDDQ
VDD
VSS
VDDSPD
DNU
NC
TYPE
Input/ Data I/Os: Data bus.
Output
DESCRIPTION
Input Serial Clock for Presence-Detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
Input Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
Input/ Serial Presence-Detect Data: SDA is a bidirectional pin used to
Output transfer addresses and data into and out of the presence-
detect device.
Supply SSTL_2 reference voltage.
Supply DQ Power Supply: +2.5V ±0.2V.
Supply Power Supply: +2.5V ±0.2V.
Supply Ground.
Supply
Serial EEPROM positive power supply: +2.3V to +3.6V.
Do Not Use: These pins are not connected on these modules,
but are assigned pins on other modules in this product family.
No Connect: These pins should be left unconnected.
pdf: 09005aef80739fa5, source: 09005aef807397e5
DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.

5 Page





MT16VDDT25664A arduino
256MB, 512MB, 1GB, 2GB (x64, DR)
184-PIN DDR SDRAM UDIMM
and reserved states should not be used because
unknown operation or incompatibility with future ver-
sions may result.
Extended Mode Register
The extended mode register controls functions
beyond those controlled by the mode register; these
additional functions are DLL enable/disable and out-
put drive strength. These functions are controlled via
the bits shown in Figure 7, Extended Mode Register
Definition Diagram. The extended mode register is
programmed via the LOAD MODE REGISTER com-
mand to the mode register (with BA0 = 1 and BA1 = 0)
and will retain the stored information until it is pro-
grammed again or the device loses power. The
enabling of the DLL should always be followed by a
LOAD MODE REGISTER command to the mode regis-
ter (BA0/BA1 both LOW) to reset the DLL.
The extended mode register must be loaded when
all device banks are idle and no bursts are in progress,
and the controller must wait the specified time before
initiating any subsequent operation. Violating either
of these requirements could result in unspecified oper-
ation.
DLL Enable/Disable
The DLL must be enabled for normal operation.
DLL enable is required during power-up initialization
and upon returning to normal operation after having
disabled the DLL for the purpose of debug or evalua-
tion. (When the device exits self refresh mode, the DLL
is enabled automatically.) Any time the DLL is enabled,
200 clock cycles with CKE HIGH must occur before a
READ command can be issued.
Figure 7: Extended Mode Register
Definition Diagram
256MB Module
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
13 12 11 10 9 8 7 6 5 4 3 2 1 0 Extended Mode
01 11
Operating Mode
DS DLL Register (Ex)
512MB and 1GB Modules
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Extended Mode
01 11
Operating Mode
DS DLL Register (Ex)
2GB Module
BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Extended Mode
01 11
Operating Mode
DS DLL Register (Ex)
E0 DLL
0 Enable
1 Disable
E1 Drive Strength
0 Normal
E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2
0 0 0 0 0 0 0 00 0 0 0
– – – – – – – –– – – –
E1, E0
Valid
Operating Mode
Reserved
Reserved
NOTE:
1. BA1 and BA0 (E13 and E12 for 256MB, E14 and E13 for
512MB, 1GB, or E15 and E14 for 2GB) must be “0, 1” to
select the Extended Mode Register (vs. the base Mode
Register).
2. QFC# is not supported.
pdf: 09005aef80739fa5, source: 09005aef807397e5
DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.

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