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PDF MT16HTF6464A Data sheet ( Hoja de datos )

Número de pieza MT16HTF6464A
Descripción 512MB DDR2 SDRAM Unbuffered DIMM
Fabricantes Micron 
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512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM
Features
DDR2 SDRAM Unbuffered DIMM
MT16HTF6464A – 512MB
MT16HTF12864A – 1GB
MT16HTF25664A – 2GB
For component specifications, refer to the Micron’s Web site: www.micron.com/ddr2
Features
• 240-pin, unbuffered, dual in-line memory module
(UDIMM)
• Fast data transfer rates: PC2-3200, PC2-4200, PC2-
5300, or PC2-6400
• 512MB (64 Meg x 64), 1GB (128 Meg x 64), and 2GB
(256 Meg x 64)
• VDD = VDDQ = +1.8V
• VDDSPD = +1.7V to +3.6V
• JEDEC standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
• Four-bit prefetch architecture
• DLL to align DQ and DQS transitions with CK
• Multiple internal device banks for concurrent
operation
• Programmable CAS latency (CL)
• Posted CAS additive latency (AL)
• WRITE latency = READ latency - 1 tCK
• Programmable burst lengths: 4 or 8
• Adjustable data-output drive strength
• 64ms, 8,192-cycle refresh
• On-die termination (ODT)
• Serial presence-detect (SPD) with EEPROM
• Gold edge contacts
• Dual rank
Figure 1: 240-Pin DIMM (MO-237 R/C “B”)
PCB height: 29.97mm (1.18in)
Options
• Package
240-pin DIMM (lead-free)
• Frequency/CL1
2.5ns @ CL = 5 (DDR2-800)2
3.0ns @ CL = 5 (DDR2-667)3
3.75ns @ CL = 4 (DDR2-533)
5.0ns @ CL = 3 (DDR2-400)
• PCB height
29.97mm (1.18in)
Marking
Y
-80E
-667
-53E
-40E
Notes: 1. CL = CAS (READ) latency.
2. Not available in 512MB density.
3. Not available in 2GB density.
PDF: 09005aef80f09084/Source: 09005aef80f09068
HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.

1 page




MT16HTF6464A pdf
512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM
Pin Assignments and Descriptions
Table 5:
Pin Descriptions
Pin numbers may not correlate with symbols; refer to Table 4 on page 3 for more information
Pin Numbers
120
Symbol
SCL
101, 239, 240
SA0–SA2
3, 4, 9, 10, 12, 13, 21, 22, 24,
25, 30, 31, 33, 34, 39, 40, 80,
81, 86, 87, 89, 90, 95, 96, 98,
99, 107, 108, 110, 111, 116,
117, 122, 123, 128, 129, 131,
132, 140, 141, 143, 144, 149,
150, 152, 153, 158, 159, 199,
200, 205, 206, 208, 209, 214,
215, 217, 218, 226, 227, 229,
230, 235, 236
6, 7, 15, 16, 27, 28, 36, 37,
83, 84, 92, 93, 104, 105, 113,
114,
DQ0–DQ63
DQS0–DQS7,
DQS0#–DQS7#
119 SDA
53, 59, 64, 67, 69, 172, 178,
184, 187, 189, 197,
51, 56, 62, 72, 75, 78, 170,
175, 181, 191, 194,
1
2, 5, 8, 11, 14, 17, 20, 23, 26,
29, 32, 35, 38, 41, 44, 47, 50,
65, 66, 79, 82, 85, 88, 91, 94,
97,100, 103, 106, 109,112,
115, 118, 121, 124, 127, 130,
133, 136, 139, 142, 145, 148,
151, 154, 157, 160, 163, 166,
169, 198, 201, 204, 207, 210,
213, 216, 219, 222, 225, 228,
231, 234, 237
238
18, 19, 42, 43, 45, 46, 48, 49,
54 (512MB, 1GB), 55, 68, 76,
102, 125, 126, 134, 135, 146,
147, 155, 156, 161, 162, 164,
165, 167, 168, 171, 173, 174,
196 (512MB), 202, 203, 211,
212, 223, 224, 232, 233
VDD
VDDQ
VREF
VSS
VDDSPD
NC
Type
Input
Input
I/O
Description
Serial clock for presence-detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
Presence-detect address inputs: These pins are used to configure
the presence-detect device.
Data Input/output: Bidirectional data bus.
I/O Data strobe: Output with read data, input with write data for
source synchronous operation. Edge-aligned with read data,
center aligned with write data. DQS# is only used when
differential data strobe mode is enabled via the LOAD MODE
command.
I/O Serial presence-detect data: SDA is a bidirectional pin used to
transfer addresses and data into and out of the presence-detect
portion of the module.
Supply Power supply: +1.8V ±0.1V.
Supply DQ Power supply: +1.8V ±0.1V.
Supply SSTL_18 reference voltage.
Supply Ground.
Supply Serial EEPROM positive power supply: +1.7V to +3.6V.
– No connect: These pins should be left unconnected.
PDF: 09005aef80f09084/Source: 09005aef80f09068
HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.

5 Page





MT16HTF6464A arduino
512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM
Electrical Specifications
Table 9:
DDR2 IDD Specifications and Conditions – 2GB
Values shown for DDR2 SDRAM components only
Parameter/Condition
Symbol
Operating one device bank active-precharge current; tCK = tCK (IDD),
tRC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between
valid commands; Address bus inputs are switching; Data bus inputs are
switching
IDD0a
Operating one device bank active-read-precharge current; IOUT =
0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS =
tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data pattern is same as
IDD4W
Precharge power-down current; All device banks idle; tCK = tCK (IDD);
CKE is LOW; Other control and address bus inputs are stable; Data bus
inputs are floating
Precharge quiet standby current; All device banks idle; tCK = tCK (IDD);
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
Precharge standby current; All device banks idle; tCK = tCK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data
bus inputs are switching
Active power-down current; All device banks open; tCK Fast PDN exit
= tCK (IDD); CKE is LOW; Other control and address bus MR[12] = 0
inputs are stable; Data bus inputs are floating
Slow PDN exit
MR[12] = 1
Active standby current; All device banks open; tCK = tCK (IDD), tRAS =
tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid
commands; Other control and address bus inputs are switching; Data bus
inputs are switching
IDD1a
IDD2Pb
IDD2Qb
IDD2Nb
IDD3Pb
IDD3Nb
Operating burst write current; All device banks open; Continuous burst
writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD),
tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address
bus inputs are switching; Data bus inputs are switching
IDD4Wa
Operating burst read current; All device banks open; Ccontinuous burst
reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data bus inputs are
switching
Burst refresh current; tCK = tCK (IDD); REFRESH command at every tRFC
(IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other
control and address bus inputs are switching; Data bus inputs are
switching
IDD4Ra
IDD5b
Self refresh current; CK and CK# at 0V; CKE 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
IDD6b
Operating device bank interleave read current; All device banks
interleaving reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 ×
tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD
(IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus
inputs are stable during DESELECTs; Data bus inputs are switching; See
IDD7 conditions in component data sheet for detail
IDD7a
-80E
856
936
112
1,040
1,120
720
160
1,200
1,536
1,576
4,480
112
2,736
-667
776
856
112
880
960
640
160
1,120
1,336
1,336
4,160
112
2,456
-53E
696
816
112
656
720
480
160
880
1,096
1,216
4,000
112
2,376
-40E
616
696
112
560
640
400
160
720
936
936
3,520
112
2,136
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes:
1. a = Value calculated as one module rank in this operating condition, and all other module
ranks in IDD2P (CKE LOW).
2. b = Value calculated reflects all module ranks in this operating condition.
PDF: 09005aef80f09084/Source: 09005aef80f09068
HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.

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