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PDF NCP5304 Data sheet ( Hoja de datos )
| Número de pieza | NCP5304 | |
| Descripción | High and Low Side Driver | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NCP5304
High Voltage, High and Low
Side Driver
The NCP5304 is a High Voltage Power gate Driver providing two
outputs for direct drive of 2 N−channel power MOSFETs or IGBTs
arranged in a half−bridge configuration.
It uses the bootstrap technique to insure a proper drive of the
High−side power switch. The driver works with 2 independent inputs
with cross conduction protection.
Features
• High Voltage Range: up to 600 V
• dV/dt Immunity ±50 V/nsec
• Negative Current Injection Characterized Over the Temperature Range
• Gate Drive Supply Range from 10 V to 20 V
• High and Low Drive Outputs
• Output Source / Sink Current Capability 250 mA / 500 mA
• 3.3 V and 5 V Input Logic Compatible
• Up to VCC Swing on Input Pins
• Extended Allowable Negative Bridge Pin Voltage Swing to −10 V
for Signal Propagation
• Matched Propagation Delays between Both Channels
• Outputs in Phase with the Inputs
• Cross Conduction Protection with 100 ns Internal Fixed Dead Time
• Under VCC LockOut (UVLO) for Both Channels
• Pin−to−Pin Compatible with Industry Standards
• These are Pb−Free Devices
Typical Applications
• Half−bridge Power Converters
• Full−bridge Converters
www.onsemi.com
1
SOIC−8
D SUFFIX
CASE 751
MARKING
DIAGRAMS
8
P5304
ALYW
G
1
1
PDIP−8
P SUFFIX
CASE 626
NCP5304
AWL
YYWWG
NCP5304 = Specific Device Code
A = Assembly Location
L or WL = Wafer Lot
Y or YY = Year
W or WW = Work Week
G or G
= Pb−Free Package
PINOUT INFORMATION
IN_LO
IN_HI
VCC
GND
18
27
36
45
VBOOT
DRV_HI
BRIDGE
DRV_LO
8 Pin Package
ORDERING INFORMATION
Device
Package
Shipping†
NCP5304PG
PDIP−8 50 Units / Rail
(Pb−Free)
NCP5304DR2G
SOIC−8 2500 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2014
November, 2014 − Rev. 7
1
Publication Order Number:
NCP5304/D
1 page  
IN_HI
NCP5304
IN_LO
DRV_HI
DRV_LO
Figure 4. Input/Output Timing Diagram
IN_HI
(IN_LO)
ton
DRV_HI
(DRV_LO)
50%
50%
tr toff
tf
90%
90%
10%
10%
Figure 5. Propagation Delay and Rise / Fall Time Definition
IN_HI
DRV_HI
IN_LO
DRV_LO
50%
50%
50%
ton_HI
10%
toff_HI
90%
Matching Delay1=ton_HI−ton_LO
Matching Delay2=toff_HI−toff_LO
50%
toff_LO
90%
Figure 6. Matching Propagation Delay
ton_LO
10%
www.onsemi.com
5
5 Page 
NCP5304
400
350 Isrc High Side
300
250
200
150 Isrc Low Side
100
50
0
10 12 14 16 18 20
VCC, VOLTAGE (V)
Figure 32. Output Source Current vs. Supply
Voltage (VCC = VBOOT)
400
350
Isrc High Side
300
250
200
150 Isrc Low Side
100
50
0
−40 −20 0
20 40 60 80 100 120
TEMPERATURE (°C)
Figure 33. Output Source Current vs.
Temperature
600
500 Isrc High Side
600
500
Isrc High Side
400
Isrc Low Side
300
200
400
300
Isrc Low Side
200
100 100
0
10 12 14 16 18
VCC, VOLTAGE (V)
Figure 34. Output Sink Current vs. Supply
Voltage (VCC = VBOOT)
20
0.2
0
−40
−20 0 20 40 60 80 100 120
TEMPERATURE (°C)
Figure 35. Output Sink Current vs.
Temperature
20
0.16
15
0.12
10
0.08
5
0.04
0
0 100 200 300 400 500 600
HV PINS VOLTAGE (V)
Figure 36. Leakage Current on High Voltage
Pins (600 V) to Ground vs. VBRIDGE Voltage
(VBRIGDE = VBOOT = VDRV_HI)
0
−40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C)
Figure 37. Leakage Current on High Voltage
Pins (600 V) to Ground vs. Temperature
(VBRIDGE = VBOOT = VDRV_HI = 600 V)
www.onsemi.com
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet NCP5304.PDF ] | |
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