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PDF SM89516A Data sheet ( Hoja de datos )
| Número de pieza | SM89516A | |
| Descripción | 8-Bit Micro-controller | |
| Fabricantes | SyncMOS | |
| Logotipo |  |
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SyncMOS Technologies Inc.
SM89516A
September 2002
Product List
SM89516AL25, 25MHz 64KB internal flash MCU
SM89516AC25, 25MHz 64KB internal flash MCU
SM89516AC40, 40MHz 64KB internal flash MCU
Description
The SM89516A series product is an 8 - bit single chip
micro controller with 64KB on-chip flash and 1K byte RAM
embedded. It is a derivative of the 8052 micro controller
family. It has 5-channel SPWM build-in. User can access
on-chip expanded RAM with easier and faster way by its
‘bank mapping direct addressing mode’ scheme. With its
hardware features and powerful instruction set, it’s
straight forward to make it a versatile and cost effective
controller for those applications which demand up to 32 I/
O pins for PDIP package or up to 36
I/O pins for PLCC/QFP package, or applications which
need up to 64K byte flash memory for program data.
To program the on-chip flash memory, a commercial writer
is available to do it in parallel programming method.
Ordering Information
yywwv
SM89516Aihhk
yy: year, ww:week
v: version identifier {, A, B,...}
i: process identifier {L=3.0V ~ 3.6V, C=4.5V ~ 5.5V}
hh: working clock in MHz {25, 40}
k: package type postfix {as below table}
v: version identifier
Features
8 - Bit Micro-controller
with 64KB flash & 1KB RAM embedded
Working voltage: 3.0V ~ 3.6V For L Version
4.5V ~ 5.5V For C Version
General 8052 family compatible
12 clocks per machine cycle
64K byte on chip program flash
1024 byte on-chip data RAM
Three 16 bit Timers/Counters
One Watch Dog Timer
Four 8-bit I/O ports for PDIP package
Four 8-bit I/O ports + one 4-bit I/O ports for PLCC or QFP package
Full duplex serial channel
Bit operation instruction
Industrial Level
8-bit Unsigned Division
8-bit Unsigned Multiply
BCD arithmetic
Direct Addressing
Indirect Addressing
Nested Interrupt
Two priority level interrupt
A serial I/O port
Power save modes: Idle mode and Power down mode
Code protection function
Low EMI (inhibit ALE)
Bank mapping direct addressing mode for access on-chip RAM
5 channel SPWM function with P1.3 ~ P1.7
Postfix
P
J
Q
Package
40L PDIP
44L PLCC
44L QFP
Pin/Pad
Configuration
page 2
page 2
page 2
Dimension
page 21
page 22
page 23
Web site: http://www.syncmos.com.tw
Specifications subject to change without notice,contact your sales representatives for the most recent information.
1/25
Taiwan
4F, No. 1 Creation Road 1,
Science-based Industrial Park,
Hsinchu, Taiwan 30077
TEL: 886-3-578-3344 #2667
886-3-579-2987
FAX: 886-3-5792960
886-3-5780493
Ver 1.2 SM89516A 09/02
1 page  
SyncMOS Technologies Inc.
September 2002
SM89516A
Special Function Register (SFR)
The address $80 to $FF can be accessed by direct addressing mode only.
Address $80 to $FF is SFR area.
The following table lists the SFRs which are identical to general 8052, as well as SM89516A Extension SFRs.
Special Function Register (SFR) Memory Map
$F8
$F0 B
$E8
$E0 ACC
$D8 P4
$D0 PSW
$C8 T2CON
$C0
T2MOD
RCAP2L
RCAP2H
TL2
TH2
$B8 IP
$B0 P3
$A8 IE
$A0 P2
$98 SCON
$90 P1
$88 TCON
$80 P0
SBUF
TMOD
SP
SCONF
SPWMD4
SPWMC SPWMD0 SPWMD1 SPWMD2 SPWMD3
P1CON
WDTC
WDTKEY
TL0 TL1 TH0 TH1
DPL
DPH
(Reserved) RCON DBANK
PCON
Note: The text of SFRs with bold type characters are Extension Special Function Registers forSM89516A
$FF
$F7
$EF
$E7
$DF
$D7
$CF
$C7
$BF
$B7
$AF
$A7
$9F
$97
$8F
$87
Addr
85H
86H
97H
9BH
9FH
A3H
A4H
A5H
A6H
A7H
ACH
BFH
C8H
C9H
D8H
SFR
Reset
RCON ******00
DBANK 0***0001
WDTKEY 00H
P1CON 00000***
WDTC 0*0**000
SPWMC ******00
SPWMD0 00H
SPWMD1 00H
SPWMD2 00H
SPWMD3 00H
SPWMD4 00H
SCONF 0*****00
T2CON 00H
T2MOD ******00
P4 ****1111
7 6 5 4 321 0
RAMS1 RAMS0
BSE
BS3 BS2 BS1 BS0
WDTKEY7 WDTKEY6 WDTKEY5 WDTKEY4 WDTKEY3 WDTKEY2 WDTKEY1 WDTKEY0
SPWME4 SPWME3 SPWME2 SPWME1 SPWME0
WDTE
CLEAR
PS2 PS1 PS0
SPFS1 SPFS0
SPWMD04 SPWMD03 SPWMD02 SPWMD01 SPWMD00 BRM02 BRM01 BRM00
SPWMD14 SPWMD13 SPWMD12 SPWMD11 SPWMD10 BRM12 BRM11 BRM10
SPWMD24 SPWMD23 SPWMD22 SPWMD21 SPWMD20 BRM22 BRM21 BRM20
SPWMD34 SPWMD33 SPWMD32 SPWMD31 SPWMD30 BRM32 BRM31 BRM30
SPWMD44 SPWMD43 SPWMD42 SPWMD41 SPWMD40 BRM42 BRM41 BRM40
WDR
OME
ALEI
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
T2OE
DCEN
P4.3
P4.2
P4.1
P4.0
Specifications subject to change without notice,contact your sales representatives for the most recent information.
5/25 Ver 1.2 SM89516A 09/02
5 Page 
SyncMOS Technologies Inc.
September 2002
SM89516A
3.Watch Dog Timer
The Watch Dog Timer (WDT) is a 16-bit free-running counter that generate reset signal if the counter overflows. The WDT is
useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing software dead
loop or runaway. The WDT function can help user software recover from abnormal software condition. The WDT is different
from Timer0, Timer1 and Timer2 of general 8052. To prevent a WDT reset can be done by software periodically clearing the
WDT counter. User should check WDR bit of SCONF register whenever un-predicted reset happened
The purpose of the secure procedure is to prevent the WDTC value from being changed when system runaway.
There is a 250KHz RC oscillator embedded in chip. Set WDTE = “1” will enable the RC oscillator and the frequency is inde-
pendent to the system frequency.
To enable the WDT is done by setting 1 to the bit 7 (WDTE) of WDTC. After WDTE set to 1, the 16-bit counter starts to count
with the RC oscillator. It will generate a reset signal when overflows. The WDTE bit will be cleared to 0 automatically when
SM59264 been reset, either hardware reset or WDT reset.
To reset the WDT is done by setting 1 to the CLEAR bit of WDTC before the counter overflow. This will clear the content of
the 16-bit counter and let the counter re-start to count from the beginning.
3.1 Watch Dog Timer Registers:
Watch Dog Timer Registers - WDT Control Register (WDTC, $9F)
bit-7 bit-0
WDTE Reserve CLEAR Unused Unused
PS2
PS1
PS0
Read / Write:
R/W
-
R/W
-
- R/W R/W R/W
Reset value:
0
*
0
*
*
000
WDTE : Watch Dog Timer enable bit
CLEAR : Watch Dog Timer reset bit
PS[2:0] : Overflow period select bits
PS [2:0]
000
001
010
011
100
101
110
111
Overflow Period (ms)
2.048
4.096
8.192
16.384
32.768
65.536
131.072
262.144
Specifications subject to change without notice,contact your sales representatives for the most recent information.
11/25
Ver 1.2 SM89516A 09/02
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet SM89516A.PDF ] | |
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