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PDF M5M465160BJ-6S Data sheet ( Hoja de datos )

Número de pieza M5M465160BJ-6S
Descripción FAST PAGE MODE DYNAMIC RAM
Fabricantes Mitsubishi 
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No Preview Available ! M5M465160BJ-6S Hoja de datos, Descripción, Manual

(Rev. 1.1)
MITSUBISHI LSIs
M5M467400/465400BJ,BTP -5,-6,-5S,-6S
M5M467800/465800BJ,BTP -5,-6,-5S,-6S
M5M465160BJ,BTP -5,-6,-5S,-6S
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
DESCRIPTION
The M5M467400/465400BJ,BTP is organized 16777216-word by 4-bit, M5M467800/465800BJ,BTP is organized 8388608-word by
8-bit, and M5M465160BJ,BTP is organized 4194304-word by 16-bit dynamic RAMs, fabricated with the high performance CMOS
process, and are suitable for large-capacity memory systems with high speed and low power dissipation.
The use of double-layer aluminum process combined with CMOS technology and a single-transistor dynamic storage stacked
capacitor cell provide high circuit density. Multiplexed address inputs permit both a reduction in pins and an increase in system
densities.
FEATURES
Type name
RAS
CAS Address OE Cycle
access access access access
time
time time
time
time
Power
dissipa-
tion
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.mW)
M5M467400BXX-5,5S
M5M467800BXX-5,5S
50
13
25
13
90 300
M5M467400BXX-6,6S
M5M467800BXX-6,6S
60
15
30
15 110 250
M5M465400BXX-5,5S
M5M465800BXX-5,5S
50
13
25
13
90 390
M5M465400BXX-6,6S
M5M465800BXX-6,6S
60
15
30
15 110 325
XX=J,TP
Type name
M5M465160BXX-5,5S
M5M465160BXX-6,6S
RAS
access
time
CAS Address OE
access access access
time time
time
Cycle
time
Power
dissipa-
tion
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.mW)
50 13 25 13 90 420
60 15 30 15 110 390
Standard 32 pin SOJ, 32 pin TSOP (M5M467400Bxx/M5M465400Bxx/M5M467800Bxx/M5M465800Bxx)
Standard 50 pin SOJ, 50 pin TSOP (M5M465160Bxx)
Single 3.3 ± 0.3V supply
Low stand-by power dissipation
1.8mW (Max)
LVCMOS input level
Low operating power dissipation
M5M467400Bxx-5,5S / M5M467800Bxx-5,5S
360.0mW (Max)
M5M467400Bxx-6,6S / M5M467800Bxx-6,6S
324.0mW (Max)
M5M465400Bxx-5,5S / M5M465800Bxx-5,5S
468.0mW (Max)
M5M465400Bxx-6,6S / M5M465800Bxx-6,6S
432.0mW (Max)
M5M465160Bxx-5,5S
504.0mW (Max)
M5M465160Bxx-6,6S
468.0mW (Max)
Self refresh capability*
Self refresh current
400µA (Max)
Fast-page mode , Read-modify-write, CAS before RAS refresh, Hidden refresh capabilities
Early-write mode and OE to control output buffer impedance
All inputs, outputs LVTTL compatible and low capacitance
* :Applicable to self refresh version(M5M467400/465400/467800/465800/465160BJ,BTP-5S,-6S:option) only
ADDRESS
Part No.
Row Add Col Add
Refresh
Refresh Cycle
Normal S-version
RAS Only Ref,Normal R/W 8192/64ms 8192/128ms
M5M467400Bxx A0-A12 A0-A10
CBR Ref,Hidden Ref
4096/64ms 4096/128ms
M5M465400Bxx
A0-A11
A0-A11
RAS Only Ref,Normal R/W
CBR Ref,Hidden Ref
4096/64ms
4096/128ms
RAS Only Ref,Normal R/W 8192/64ms 8192/128ms
M5M467800Bxx A0-A12 A0-A9
CBR Ref,Hidden Ref
4096/64ms 4096/128ms
M5M465800Bxx
A0-A11
A0-A10
RAS Only Ref,Normal R/W
CBR Ref,Hidden Ref
4096/64ms
4096/128ms
M5M465160Bxx A0-A11 A0-A9
RAS Only Ref,Normal R/W
CBR Ref,Hidden Ref
4096/64ms
4096/128ms
APPLICATION
Main memory unit for computers, Microcomputer memory, Refresh memory for CRT
1
MITSUBISHI
Jun. 1999
ELECTRIC

1 page




M5M465160BJ-6S pdf
(Rev. 1.1)
MITSUBISHI LSIs
M5M467400/465400BJ,BTP -5,-6,-5S,-6S
M5M467800/465800BJ,BTP -5,-6,-5S,-6S
M5M465160BJ,BTP -5,-6,-5S,-6S
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
M5M467400Bxx / M5M465400Bxx
BLOCK DIAGRAM
COLUMN ADDRESS
STROBE INPUT
ROW ADDRESS
STROBE INPUT
CAS
RAS
WRITE CONTROL W
INPUT
ADDRESS INPUTS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
(Note)
CLOCK GENERATOR
CIRCUIT
A0~A11
(Note)
COLUMN DECODER
SENSE REFRESH
AMPLIFIER & I /O CONTROL
A0~
A12
(Note)
MEMORY CELL
(67108864 BITS)
Note : Refer to Page 1 (ADDRESS)
Vcc (3.3V)
Vss (0V)
DQ1
DQ2
DQ3
DQ4
DATA
INPUTS / OUTPUTS
OE OUTPUT ENABLE
INPUT
M5M467800Bxx / M5M465800Bxx
BLOCK DIAGRAM
COLUMN ADDRESS
STROBE INPUT
ROW ADDRESS
STROBE INPUT
CAS
RAS
WRITE CONTROL W
INPUT
ADDRESS INPUTS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
(Note)
CLOCK GENERATOR
CIRCUIT
A0~A10
(Note)
COLUMN DECODER
SENSE REFRESH
AMPLIFIER & I /O CONTROL
A0~
A12
(Note)
MEMORY CELL
(67108864 BITS)
Note : Refer to Page 1 (ADDRESS)
Vcc (3.3V)
Vss (0V)
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DATA
INPUTS / OUTPUTS
OE OUTPUT ENABLE
INPUT
5
MITSUBISHI
Jun. 1999
ELECTRIC

5 Page





M5M465160BJ-6S arduino
(Rev. 1.1)
MITSUBISHI LSIs
M5M467400/465400BJ,BTP -5,-6,-5S,-6S
M5M467800/465800BJ,BTP -5,-6,-5S,-6S
M5M465160BJ,BTP -5,-6,-5S,-6S
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Write Cycle (Early Write and Delayed Write)
Symbol
Parameter
tWC
tRAS
tCAS
tCSH
tRSH
tWCS
tWCH
tCWL
tRWL
tWP
tDS
tDH
tOEH
Write cycle time
RAS low pulse width
CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Write setup time before CAS low
(Note 23)
Write hold time after CAS low
CAS hold time after W low
RAS hold time after W low
Write pulse width
Data setup time before CAS low or W low
Data hold time after CAS low or W low
OE hold time after W low
Limits
M5M46X400B-5,5S M5M46X400B-6,6S
M5M46X800B-5,5S M5M46X800B-6,6S
M5M465160B-5,5S M5M465160B-6,6S
Unit
Min Max Min Max
90 110 ns
50 10000
60 10000 ns
13 10000
15 10000 ns
50 60 ns
13 15 ns
0 0 ns
8 10 ns
13 15 ns
13 15 ns
8 10 ns
0 0 ns
8 10 ns
13 15 ns
Read-Write and Read-Modify-Write Cycles
Symbol
Parameter
tRWC
tRAS
tCAS
tCSH
tRSH
tRCS
tCWD
tRWD
tAWD
tCWL
tRWL
tWP
tDS
tDH
tOEH
Read write/read modify write cycle time
RAS low pulse width
CAS low pulse width
(Note22)
CAS hold time after RAS low
RAS hold time after CAS low
Read setup time before CAS low
Delay time, CAS low to W low
Delay time, RAS low to W low
Delay time, address to W low
CAS hold time after W low
RAS hold time after W low
(Note23)
(Note23)
(Note23)
Write pulse width
Data setup time before CAS low or W low
Data hold time after CAS low or W low
OE hold time after W low
Limits
M5M46X400B-5,5S M5M46X400B-6,6S
M5M46X800B-5,5S M5M46X800B-6,6S
M5M465160B-5,5S M5M465160B-6,6S
Unit
Min Max Min Max
126 150 ns
85 10000
95 10000 ns
50 10000
50 10000 ns
85 95 ns
50 50 ns
0 0 ns
30 30 ns
65 75 ns
40 45 ns
13 15 ns
13 15 ns
8 10 ns
0 0 ns
8 10 ns
13 15 ns
Note 22: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT.
23: tWCS, tCWD, tRWD and tAWD and, tCPWD are specified as reference points only. If tWCS tWCS(min) the cycle is an early write cycle and the
DQ pins will remain high impedance throughout the entire cycle. If tCWD tCWD(min), tRWD tRWD (min), tAWD tAWD(min) and tCPWD tCPWD(min)
(for Fast Page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address.
If neither of the above condition (delayed write) is satisfied, the DQ (at access time and until CAS or OE goes back to VIH ) is indetermi-
nate.
11
MITSUBISHI
Jun. 1999
ELECTRIC

11 Page







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