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PDF M5M4V4405CJ-6 Data sheet ( Hoja de datos )

Número de pieza M5M4V4405CJ-6
Descripción EDO (HYPER PAGE MODE) 4M-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
Fabricantes Mitsubishi 
Logotipo Mitsubishi Logotipo



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MITSMUIBTSISUHBI ISLHSIsLSIs
M5M4V4405MC5JM,4TVP44-065,C-J7,T,-P6-6S,-7,,--76SS,-7S
EDOE(DHOYP(HEYRPPEARGPEAMGOEDMEO) D41E9)44310944-3B0I4T-B(1I0T4(180547865-W76O-WRDORBDY B4-YB4IT-B) DITY)NDAYMNIACMRICAMRAM
DESCRIPTION
This is a family of 1048576-word by 4-bit dynamic RAMS,
fabricated with the high performance CMOS process,and is ideal
for large-capacity memory systems where high speed, low power
dissipation , and low costs are essential.
The use of quadruple-layer polysilicon process combined with
silicide technology and a single-transistor dynamic storage stacked
capacitor cell provide high circuit density at reduced costs.
Multiplexed address inputs permit both a reduction in pins and an
increase in system densities.
Self or extended refresh current is low enough for battery
back-up application.
PIN CONFIGURATION (TOP VIEW)
DQ1 1
DQ2 2
W3
RAS 4
A9 5
26 VSS
25 DQ4
24 DQ3
23 CAS
22 OE
FEATURES
Type name
RAS CAS Address OE
access access access access
time time time time
Cycle
Power
dissipa-
time tion
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.mW)
M5M4V4405CXX-6, -6S 60 15 30 15 110 264
M5M4V4405CXX-7, -7S 70 20 35 20 130 231
XX=J, TP
Standard 26 pin SOJ, 26 pin TSOP(II)
Single 3.3V±0.3V supply
Low stand-by power dissipation
CMOS lnput level .................................................1.8mW(Max)*
CMOS lnput level ................................................180µW(Max)
Low operating power dissipation
M5M4V4405Cxx-6, -6S .....................................288.0mW (Max)
M5M4V4405Cxx-7, -7S ....................................252.0mW (Max)
Self refresh capabiility*
Self refresh current ..............................................100µA(max)
Extended refresh capability*
Extended refresh current ....................................100µA(max)
Hyper-page mode (1024-bit random access), Read-modify- write,
RAS-only refresh CAS before RAS refresh, Hidden refresh, CBR
self refresh(-6S,-7S) capabilities.
Early-write mode and OE and W to control output buffer impedance
1024 refresh cycles every 16.4ms (A0~A9)
1024refresh cycle every128ms (A0~A9)*
*: Applicable to self refresh version (M5M4V4405Cxx-6S,-7S:
option) only
APPLICATION
Lap top personal computer,Solid state disc, Microcomputer
memory, Refresh memory for CRT
A0 9
A1 10
A2 11
A3 12
VCC 13
18 A8
17 A7
16 A6
15 A5
14 A4
Outline 26P0J (300mil SOJ)
DQ1 1
DQ2 2
W3
RAS 4
A9 5
26 VSS
25 DQ4
24 DQ3
23 CAS
22 OE
A0 9
A1 10
A2 11
A3 12
VCC 13
18 A8
17 A7
16 A6
15 A5
14 A4
Outline 26P3Z-E (300mil TSOP)
PIN DESCRIPTION
Pin name
A0~A9
DQ1~DQ4
RAS
CAS
W
OE
VCC
VSS
Function
Address inputs
Data inputs / outputs
Row address strobe input
Column address strobe input
Write control input
Output enable input
Power supply (+3.3V)
Ground (0V)
1

1 page




M5M4V4405CJ-6 pdf
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh, and Hyper-Page Mode Cycles)
(Ta=0~70˚C, VCC = 3.3V±0.3V, VSS =0V, unless otherwise noted, see notes 14,15)
Symbol
Parameter
tREF
tREF
tRP
tRCD
tCRP
tRPC
tCPN
tRAD
tASR
tASC
tRAH
tCAH
tDZC
tDZO
tRDD
tCDD
tODD
tT
Refresh cycle time
Refresh cycle time*
RAS high pulse width
Delay time, RAS low to CAS low
Delay time, CAS high to RAS low
Delay time, RAS high to CAS low
CAS high pulse width
Column address delay time from RAS low
Row address setup time before RAS low
Column address setup time before CAS low
Row address hold time after RAS low
Column address hold time after CAS low
Delay time, data to CAS low
Delay time, data to OE low
Delay time, RAS high to data
Delay time, CAS high to data
Delay time, OE high to data
Transition time
(Note 16)
(Note 17)
(Note 18)
(Note 19)
(Note 19)
(Note 20)
(Note 20)
(Note 20)
(Note 21)
Limits
M5M4V4405C-6,-6S M5M4V4405C-7,-7S
Min Max Min Max
16.4
128
40
16.4
128
50
20 45 20 50
55
00
10 13
15 30 15 35
0
0 13
0
0 13
10 10
10 10
00
00
15 20
15 20
15 20
1 50
1 50
Unit
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 14: The timing requirements are assumed tT =2ns.
Å@ 15: VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
Å@ 16: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is
controlled exclusively by tCAC or tAA.
Å@ 17: tRAD(max) is specified as a reference point only. If tRAD tRAD(max) and tASC tASC(max), access time is controlled exclusively by tAA.
Å@ 18: tASC(max) is specified as a reference point only. If tRCD tRCD(max) and tASC tASC(max), access time is controlled exclusively by tCAC.
Å@ 19: Either tDZC or tDZO must be satisfied.
Å@ 20: Either tRDD or tCDD or tODD must be satisfied.
Å@ 21: tT is measured between VIH(min) and VIL(max).
Read and Refresh Cycles
Symbol
Parameter
tRC Read cycle time
tRAS RAS low pulse width
tCAS CAS low pulse width
tCSH CAS hold time after RAS low
tRSH RAS hold time after CAS low
tRCS Read Setup time before CAS low
tRCH
Read hold time after CAS high
tRRH
Read hold time after RAS high
tRAL Column address to RAS hold time
tCAL Column address to CAS hold time
tORH
RAS hold time after OE low
tOCH
CAS hold time after OE low
Note 22: Either tRCH or tRRH must be satisfied for a read cycle.
(Note 22)
(Note 22)
Limits
M5M4V4405C-6,-6S M5M4V4405C-7,-7S
Min Max Min Max
110 130
60 10000 70 10000
10 10000 13 10000
48 55
15 20
00
00
00
30 35
18 23
15 20
15 20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5

5 Page





M5M4V4405CJ-6 arduino
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
Early Write Cycle
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
RAS
VIH
VIL
CAS
VIH
VIL
A0~A9
VIH
VIL
VIH
W
VIL
DQ1~DQ4
(INPUTS)
VIH
VIL
tWC
tRAS
tCRP
tRCD
tCSH
tRSH
tCAS
tASR
tRAH
ROW
ADDRESS
tASC
tCAH
COLUMN
ADDRESS
tWCS
tWCH
tDH
tDS
DATA VALID
tRP
tCRP
tASR
ROW
ADDRESS
DQ1~DQ4
(OUTPUTS)
VOH
VOL
VIH
OE
VIL
Hi-Z

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