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PDF M5M4V4265CJ-6 Data sheet ( Hoja de datos )

Número de pieza M5M4V4265CJ-6
Descripción EDO 4M-Bit DRAM
Fabricantes Mitsubishi 
Logotipo Mitsubishi Logotipo



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No Preview Available ! M5M4V4265CJ-6 Hoja de datos, Descripción, Manual

MITMSUITBSIUSHBISLHSIIsLSIs
M5M4V4265CJM,5TMP4V-452,6-56C,J-,7TP,--55,-S6,,--76,-5SS,,--67SS,-7S
EDOED(HOY(PHEYRPPEARGPEA)GMEO) DMEO4D1E9431094-3B0I4T-B(2IT62(124642-1W44O-WRDORBDY 1B6Y-B1I6T-)BDITY)NDAYMNIACMRICAMRAM
DESCRIPTION
This is a family of 262144-word by 16-bit dynamic RAMs with EDO
mode fuction, fabricated with the high performance CMOS
process, and is ideal for the buffer memory systems of personal
computer graphics and HDD where high speed, low power
dissipation, and low costs are essential. The use of double-layer
metalization process technology and a single-transistor dynamic
storage stacked capacitor cell provide high circuit density at
reduced costs. The lower supply (3.3V) operation, due to the
optimization of transistor structure, provides low power dissipation
while maintaining high speed operation. Multiplexed address inputs
permit both a reduction in pins and an increase in system
densities. Self or extended refresh current is low enough for
battery back-up application. This device has 2CAS and 1W
terminals with a refresh cycle of 512 cycles every 8.2ms.
FEATURES
Type name
RAS
CAS Address
access access access
time time time
OE Cycle
access
time
time
Power
dissipa-
tion
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.mW)
M5M4V4265CXX-5,-5S 50
13
25 13
90 408
M5M4V4265CXX-6,-6S 60 15 30 15 110 363
M5M4V4265CXX-7,-7S 70 20 35 20 130 333
XX=TP,J
Standard 40 pin SOJ, 44 pin TSOP (II)
Single 3.3±0.3V supply
Low stand-by power dissipation
CMOS Input level
1.8mW (Max)
CMOS Input level
360µW (Max) *
Operating power dissipation
M5M4V4265CXX-5,-5S
486mW (Max)
M5M4V4265CXX-6,-6S
432mW (Max)
M5M4V4265CXX-7,-7S
396mW (Max)
Self refresh capability *
Self refresh current
100µA (Max)
Extended refresh capability
Extended refresh current
100µA (Max)
EDO mode (512-column random access), Read-modify-write, RAS-
only refresh, CAS before RAS refresh, Hidden refresh capabilities.
Early-write mode, OE and W to control output buffer impedance
512 refresh cycles every 8.2ms (A0~A8)
512 refresh cycles every 128ms (A0~A8) *
Byte or word control for Read/Write operation (2CAS, 1W type)
* : Applicable to self refresh version (M5M4V4265CJ,TP-5S,-6S,
-7S : option) only
APPLICATION
Microcomputer memory, Refresh memory for CRT, Frame buffer
memory for CRT
PIN DESCRIPTION
Pin name
A0~A8
DQ1~DQ16
RAS
LCAS
Function
Address inputs
Data inputs / outputs
Row address strobe input
Lower byte control
column address strobe input
UCAS
Upper byte control
column address strobe input
W Write control input
OE Output enable input
VCC Power supply (+3.3V)
VSS Ground (0V)
1
M5M4V4265CJ,TP-5,-5S:under development
PIN CONFIGURATION (TOP VIEW)
(3.3V)VCC 1
DQ1 2
DQ2 3
DQ3 4
DQ4 5
(3.3V)VCC 6
DQ5 7
DQ6 8
DQ7 9
DQ8 10
NC 11
NC 12
W 13
RAS 14
NC 15
A0 16
A1 17
A2 18
A3 19
(3.3V)VCC 20
40 VSS(0V)
39 DQ16
38 DQ15
37 DQ14
36 DQ13
35 VSS(0V)
34 DQ12
33 DQ11
32 DQ10
31 DQ9
30 NC
29 LCAS
28 UCAS
27 OE
26 A8
25 A7
24 A6
23 A5
22 A4
21 VSS(0V)
Outline 40P0K (400mil SOJ)
(3.3V)VCC 1
DQ1 2
DQ2 3
DQ3 4
DQ4 5
(3.3V)VCC 6
DQ5 7
DQ6 8
DQ7 9
DQ8 10
44 VSS(0V)
43 DQ16
42 DQ15
41 DQ14
40 DQ13
39 VSS(0V)
38 DQ12
37 DQ11
36 DQ10
35 DQ9
NC 13
NC 14
W 15
RAS 16
NC 17
A0 18
A1 19
A2 20
A3 21
(3.3V)VCC 22
32 NC
31 LCAS
30 UCAS
29 OE
28 A8
27 A7
26 A6
25 A5
24 A4
23 VSS(0V)
Outline 44P3W-R (400mil TSOP Nomal Bend)
NC : NO CONNECTION

1 page




M5M4V4265CJ-6 pdf
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh and EDO Mode Cycles)
(Ta=0~70˚C, VCC=3.3±0.3V, VSS=0V, unless otherwise noted, see notes 14,15)
Limits
Symbol
Parameter
M5M4V4265C-5,-5S M5M4V4265C-6,-6S M5M4V4265C-7,-7S
Unit
Min Max Min Max Min Max
tREF Refresh cycle time
8.2 8.2 8.2 ms
tREF
tRP
tRCD
tCRP
tRPC
tCPN
tRAD
Refresh cycle time *
RAS high pulse width
Delay time, RAS low to CAS low
Delay time, CAS high to RAS low
Delay time, RAS high to CAS low
CAS high pulse width
Column address delay time from RAS low
128 128 128
30 40 50
(Note 16) 18
32 20
45 20
50
5 55
0 00
8 10 10
(Note 17) 13 25 15
30 15
35
ms
ns
ns
ns
ns
ns
ns
tASR Row address setup time before RAS low
0 00
ns
tASC
Column address setup time before CAS low
(Note 18) 0
10
0 13
0
13
ns
tRAH Row address hold time after RAS low
8 10 10
tCAH Column address hold time after CAS low
8 10 10
tDZC Delay time, data to CAS low
(Note 19) 0
00
tDZO Delay time, data to OE low
(Note 19) 0
00
tRDD
Delay time, RAS high to data
(Note 20) 13 15 20
tCDD
Delay time, CAS high to data
(Note 20) 13 15 20
ns
ns
ns
ns
ns
ns
tODD
tT
Delay time, OE high to data
Transition time
(Note 20)
(Note 21)
13
1
15
50 1
20
50 1
50
ns
ns
Note 14 : The timing requirements are assumed tT=2ns.
Note 15 : VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
Note 16 : tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is
controlled exclusively by tCAC or tAA.
Note 17 : tRAD(max) is specified as a reference point only. If tRADtRAD(max) and tASCtASC(max), access time is controlled exclusively by tAA.
Note 18 : tASC(max) is specified as a reference point only. If tRCDtRCD(max) and tASCtASC(max), access time is controlled exclusively by tCAC.
Note 19 : Either tDZC or tDZO must be satisfied.
Note 20 : Either tRDD or tCDD or tODD must be satisfied.
Note 21 : tT is measured between VIH(min) and VIL(max).
Read and Refresh Cycles
Symbol
Parameter
tRC Read cycle time
tRAS RAS low pulse width
tCAS CAS low pulse width
tCSH CAS hold time after RAS low
tRSH RAS hold time after CAS low
tRCS Read setup time before CAS low
tRCH
Read hold time after CAS high
tRRH
Read hold time after RAS high
tRAL Column address to RAS hold time
tCAL Column address to CAS hold time
tORH
RAS hold time after OE low
tOCH
CAS hold time after OE low
Note 22 : Either tRCH or tRRH must be satisfied for a read cycle.
(Note 22)
(Note 22)
M5M4V4265C-5,-5S
Min Max
90
50 10000
8 10000
40
13
0
0
0
25
13
13
13
Limits
M5M4V4265C-6,-6S
Min Max
110
60 10000
10 10000
48
15
0
0
0
30
18
15
15
M5M4V4265C-7,-7S
Min Max
130
70 10000
13 10000
55
20
0
0
0
35
23
20
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
M5M4V4265CJ,TP-5,-5S:under development

5 Page





M5M4V4265CJ-6 arduino
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Byte Early Write Cycle
RAS
VIH
VIL
LCAS
(or UCAS)
VIH
VIL
UCAS
(or LCAS)
VIH
VIL
A0~A8
VIH
VIL
VIH
W
VIL
tCRP
tRCD
tWC
tRAS
tCSH
tRSH
tCAS
tASR tRAH
ROW
ADDRESS
tASC
tCAH
COLUMN
ADDRESS
tWCS
tWCH
tRP
tRPC
tCRP
tASR
ROW
ADDRESS
DQ1~DQ8 VIH
(or DQ9~DQ16)
(INPUTS) VIL
DQ1~DQ8 VOH
(or DQ9~DQ16)
(OUTPUTS) VOL
(DoQr 9D~QD1Q~1D6Q8)VIH
(INPUTS) VIL
DQ9~DQ16 VOH
(or DQ1~DQ8)
(OUTPUTS) VOL
Hi-Z
tDS tDH
DATA VALID
Hi-Z
VIH
OE
VIL
11
M5M4V4265CJ,TP-5,-5S:under development

11 Page







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