DataSheet.es    


PDF M5M465805DJ-5S Data sheet ( Hoja de datos )

Número de pieza M5M465805DJ-5S
Descripción EDO MODE DYNAMIC RAM
Fabricantes Mitsubishi 
Logotipo Mitsubishi Logotipo



Hay una vista previa y un enlace de descarga de M5M465805DJ-5S (archivo pdf) en la parte inferior de esta página.


Total 30 Páginas

No Preview Available ! M5M465805DJ-5S Hoja de datos, Descripción, Manual

(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
PRELIMINARY
Some of contents are subject to change without notice.
DESCRIPTION
The M5M467405/465405DJ,DTP is a 16777216-word by 4-bit, M5M467805/465805DJ,DTP is a 8388608-word by 8-bit, and
M5M465165DJ,DTP is a 4194304-word by 16-bit dynamic RAMs, fabricated with the high performance CMOS process, and are
suitable for large-capacity memory systems with high speed and low power dissipation.
FEATURES
Type name
RAS
CAS Address OE Cycle
access access access access
time
time time
time
time
Power
dissipa-
tion
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.mW)
M5M467405DXX-5,5S
M5M467805DXX-5,5S
50
13
25
13
84 300
M5M467405DXX-6,6S
M5M467805DXX-6,6S
60
15
30
15 104 250
M5M465405DXX-5,5S
M5M465805DXX-5,5S
50
13
25
13
84 390
M5M465405DXX-6,6S
M5M465805DXX-6,6S
60
15
30
15 104 325
XX=J,TP
Type name
M5M465165DXX-5,5S
M5M465165DXX-6,6S
RAS
CAS Address OE
access access access access
time
time time
time
Cycle
time
Power
dissipa-
tion
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.mW)
50 13 25 13 84 420
60 15 30 15 104 390
Standard 32 pin SOJ, 32 pin TSOP (M5M467405Dxx/M5M465405Dxx/M5M467805Dxx/M5M465805Dxx)
Standard 50 pin SOJ, 50 pin TSOP (M5M465165Dxx)
Single 3.3 ± 0.3V supply
Low stand-by power dissipation
1.8mW (Max)
LVCMOS input level
Low operating power dissipation
M5M467405Dxx-5,5S / M5M467805Dxx-5,5S
360.0mW (Max)
M5M467405Dxx-6,6S / M5M467805Dxx-6,6S
324.0mW (Max)
M5M465405Dxx-5,5S / M5M465805Dxx-5,5S
468.0mW (Max)
M5M465405Dxx-6,6S / M5M465805Dxx-6,6S
432.0mW (Max)
M5M465165Dxx-5,5S
504.0mW (Max)
M5M465165Dxx-6,6S
468.0mW (Max)
Self refresh capability*
Self refresh current
400µA (Max)
EDO mode , Read-modify-write, CAS before RAS refresh, Hidden refresh capabilities
Early-write mode , OE and W to control output buffer impedance
All inputs, outputs LVTTL compatible and low capacitance
* :Applicable to self refresh version(M5M467405/465405/467805/465805/465165DJ,DTP-5S,-6S:option) only
ADDRESS
Part No.
Row Add. Col. Add.
Refresh
Refresh Cycle
Normal S-version
RAS Only Ref,Normal R/W 8192/64ms 8192/128ms
M5M467405Dxx A0-A12 A0-A10
CBR Ref,Hidden Ref
4096/64ms 4096/128ms
M5M465405Dxx A0-A11
A0-A11
RAS Only Ref,Normal R/W
CBR Ref,Hidden Ref
4096/64ms
4096/128ms
M5M467805Dxx A0-A12 A0-A9
RAS Only Ref,Normal R/W 8192/64ms 8192/128ms
CBR Ref,Hidden Ref
4096/64ms 4096/128ms
M5M465805Dxx A0-A11
M5M465165Dxx A0-A11
A0-A10
A0-A9
RAS Only Ref,Normal R/W
CBR Ref,Hidden Ref
4096/64ms
4096/128ms
RAS Only Ref,Normal R/W
CBR Ref,Hidden Ref
4096/64ms
4096/128ms
APPLICATION
Main memory unit for computers, Microcomputer memory, Refresh memory for CRT
1 Aug. 1999
MITSUBISHI ELECTRIC

1 page




M5M465805DJ-5S pdf
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
M5M467405Dxx / M5M465405Dxx
BLOCK DIAGRAM
COLUMN ADDRESS
STROBE INPUT
ROW ADDRESS
STROBE INPUT
CAS
RAS
WRITE CONTROL W
INPUT
ADDRESS INPUTS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
(Note)
CLOCK GENERATOR
CIRCUIT
A0~A11
(Note)
COLUMN DECODER
SENSE REFRESH
AMPLIFIER & I /O CONTROL
A0~
A12
(Note)
MEMORY CELL
(67108864 BITS)
Note : Refer to Page 1 (ADDRESS)
M5M467805Dxx / M5M465805Dxx
BLOCK DIAGRAM
COLUMN ADDRESS
STROBE INPUT
ROW ADDRESS
STROBE INPUT
CAS
RAS
WRITE CONTROL W
INPUT
ADDRESS INPUTS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
(Note)
CLOCK GENERATOR
CIRCUIT
A0~A10
(Note)
COLUMN DECODER
SENSE REFRESH
AMPLIFIER & I /O CONTROL
A0~
A12
(Note)
MEMORY CELL
(67108864 BITS)
Note : Refer to Page 1 (ADDRESS)
Vcc (3.3V)
Vss (0V)
DQ1
DQ2
DQ3
DQ4
DATA
INPUTS / OUTPUTS
OE OUTPUT ENABLE
INPUT
Vcc (3.3V)
Vss (0V)
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DATA
INPUTS / OUTPUTS
OE OUTPUT ENABLE
INPUT
5 Aug. 1999
MITSUBISHI ELECTRIC

5 Page





M5M465805DJ-5S arduino
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Write Cycle (Early Write and Delayed Write)
Symbol
Parameter
tWC
tRAS
tCAS
tCSH
tRSH
tWCS
tWCH
tCWL
tRWL
tWP
tDS
tDH
Write cycle time
RAS low pulse width
CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Write setup time before CAS low
(Note 24)
Write hold time after CAS low
CAS hold time after W low
RAS hold time after W low
Write pulse width
Data setup time before CAS low or W low
Data hold time after CAS low or W low
Limits
M5M46X405D-5,5S M5M46X405D-6,6S
M5M46X805D-5,5S M5M46X805D-6,6S
M5M465165D-5,5S M5M465165D-6,6S
Min Max Min Max
84 104
50 10000 60 10000
8 10000 10 10000
35 40
13 15
00
8 10
8 10
8 10
8 10
00
8 10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read-Write and Read-Modify-Write Cycles
Symbol
Parameter
tRWC
tRAS
tCAS
tCSH
tRSH
tRCS
tCWD
tRWD
tAWD
tOEH
Read write/read modify write cycle time
RAS low pulse width
CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Read setup time before CAS low
Delay time, CAS low to W low
Delay time, RAS low to W low
Delay time, address to W low
OE hold time after W low
(Note23)
(Note24)
(Note24)
(Note24)
Limits
M5M46X405D-5,5S M5M46X405D-6,6S
M5M46X805D-5,5S M5M46X805D-6,6S Unit
M5M465165D-5,5S M5M465165D-6,6S
Min Max Min Max
109 133 ns
75 10000
89 10000 ns
38 10000
70
44 10000 ns
82 ns
38 44 ns
0 0 ns
28 32 ns
65 77 ns
40 47 ns
13 15 ns
Note 23: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT.
24: tWCS, tCWD, tRWD and tAWD and, tCPWD are specified as reference points only. If tWCS tWCS(min) the cycle is an early write cycle and the
DQ pins will remain high impedance throughout the entire cycle. If tCWD tCWD(min), tRWD tRWD (min), tAWD tAWD(min) and tCPWD tCPWD(min)
(for EDO mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address.
If neither of the above condition (delayed write) is satisfied, the DQ (at access time and until CAS or OE goes back to VIH ) is indetermi-
nate.
11 Aug. 1999
MITSUBISHI ELECTRIC

11 Page







PáginasTotal 30 Páginas
PDF Descargar[ Datasheet M5M465805DJ-5S.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
M5M465805DJ-5EDO MODE DYNAMIC RAMMitsubishi
Mitsubishi
M5M465805DJ-5SEDO MODE DYNAMIC RAMMitsubishi
Mitsubishi

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar