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PDF M5M4257S-20 Data sheet ( Hoja de datos )
| Número de pieza | M5M4257S-20 | |
| Descripción | 256K-Bit DRAM | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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MITSUBISHI LSls
MSM42S7S·12, -15, -20
262 i44-BIT (262 i44-WORD BY i-BIT) DYNAMIC RAM
DESCRIPTION
This is a family of 262 l44-word by l-bit dynamic RAMs,
fabricated with the high performance N-channel silicon gate
MOS process, and is ideal for large-capacity memory
systems where high speed, low power dissipation, and low
costs are essential. The use of double-layer polysilicon
process combined with silicide technology and a single-
transistor dynamic storage cell provide high circuit density
at reduced costs, and the use of dynamic circuitry including
sense amplifiers assures low power dissipation. Multiplexed
address inputs permit both a reduction in pins to the stand-
ard l6-pin package configuration and an increase in system
densities. In addition to the RAS only refresh mode, the
Hidden refresh mode and CAS before RAS refresh mode
are available.
FEATURES
Type name
Access time
(max)
(ns)
Cycle time
(min)
(ns)
Power dissipation
(typ)
(mW)
M5M4257S-12
120
230
260
M5M4257S-15
150
260
230
M5M4257S-20
200
330
190
• Standard l6-pm package
• Single 5V±10% supply
• Low standby power dissipation: 22mW (max)
• Low operating power dissipation:
M5M4257S-12 ........... 413mW (max)
M5M4257S-15 ........... 385mW (max)
M5M4257S-20 ........... 303mW (max)
• Unlatched output enables two-dimensional chip selec-
tion
PIN CONFIGURATION (TOP VIEW)
ADDRESS INPUT As'" I
DATA INPUT
WRITE
CONTROL INPUT
ROW ADDRESS RAS -+ 4
STRO::~::~:1:: ::
INPUTS
A1 .... 7
(5V) Vee
Vss (OV)
15 ... CAS mg~~ I~~B~ESS
DATA OUTPUT
Outline 16S1
• Early-write operation gives common I/O capability
• Read-modify-write, RAS-only-refresh, Nibble-mode
capabilities. (Pin 1 is used for nibble mode)
• CAS before RAS refresh mode capability
• All input terminals have low input capacitance and are
directly TTL-compatible
• Output is three-state and directly TTL-compatible
• 256 refresh cycles every 4ms. Pin 1 is not needed for
refresh.
• CAS controlled output allows hidden refresh
APPLICATION
• Main memory unit for computers
• Microcomputer memory
BLOCK DIAGRAM
DATA INPUT
WR ITE CONTROL
INPUT
0 2 r--------------------------,
w 3r--------------~
I
~Vee(5V)
ADDRESS
INPUTS
I
1V~(",J
cr;
a:
32K w
32K
a:
32K w
32K
oill
8A2
MEMORY
ARRAY
0
u0
w
MEMORY
ARRAY
MEMORY
ARRAY
0
u0
w
MEMORY
ARRAY
oill
0
0
ill
-!
A3 ~S=====~~=====F====~_+=====t_Jz''""
A4
As
~t=====~COiLUrM=N ====F====~DE_COtDE,R====~_,~>'u5-
'" '" 8A6
~------,_g JA7
32K 32K 32K 32K
MEMORY
ARRAY
0
a:
MEMORY MEMORY
ARRAY
ARRAY
a0:
MEMORY
ARRAY
o-!
cr;
z>-
I
• MITSUBISHI
.... ELECTRIC
2-125
1 page  
MITSUBISHI LSls
M5M4257S-12, -15, -20
262 i44-BIT (262 i44-WORD BY i-BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh, and Nibble-Mode Cycle)
( Ta = 0 -7o g e, Vee = sv ± 10%, Vss = OV. unless otherwise noted, See notes 5, 6 and 7)
Symbol
Parameter
ICAF
I W(RASH)
IW(RASL)
IW(CASL)
I W(CASH)
Ih (AAS-CAS)
Ih (CAS-AAS)
Id (CAS-RAS)
Id (RAS-CAS)
Isu (AA-AAS)
Isu (CA-CAS)
Ih (AAS-RA)
Ih (CAS-CA)
Ih (RAS-CA)
I THL
I TLH
Refresh cycle time
RAS high pulse width
RAS low pulse width
CAS low pulse width
CAS high pulse width
CAS hold time after RAS
RAS hold time after CAS
Delay time, CAS to RAS
Delay time, RAS to CAS'
Row address setup time before RAS
Column address setup time before CAS
Row address hold time after FfA."S
Column address hold lime after CAS
Column address hold time after RAS
Transition time
INote 8)
INote 9)
(Note 10)
Alternative
Symbol
IREF
IRP
I RAS
ICAS
t CPN
ICSH
I RSH
t CAP
I ACO
IASA
IASC
I RAH
I CAH
I AR
IT
M5M4257S-12
Min Max
4
100
120 10000
60
30
120
60
30
25 60
0
0
15
20
80
Limits
M5M4257S-15
Min Max
4
100
150 10000
75
35
150
75
30
25 75
0
-5
20
25
100
M5M4257S-20
Min Max
4
120
200 10000
100
40
200
100
40
30 100
0
-5
25
35
135
3 50 3 50 3 50
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 5
6
10
An initial pause of SOOps is required after power-up followed by any eight RAS or RASICAS cycles before proper device operation is achieved.
The switching characteristics are defined as t THL =t TLH =5n5.
Reference levels of input signals are V, H min. and VI L max. Reference levels for transition time are also between V IH and VI L.
Except for nibble-mode.
td (RAS-CAS) requirement is applicable for all AAS/CAS cycles
Operation within the td (RAS-CAS) max limit insures that ta (RAS) max can be met. td (RAS-CAS)maX is specified reference point only;if
td (RAS-CAS) is greater than the specified td (RAS-CAS) max limit, then access time is controlled exclusively by ta (CAS)'
+ +td (RAS- CAS)mln = t h (RAS-RA)mm 2t THL (t Tu.d t SU (CA-CAS)mln.
SWITCHING CHARACTERISTICS (Ta=0-70·C. Vcc=5V±10%, Vss=OV, unless otherwise noted)
Read Cycle
Symbol
Parameter
Alternative
Symbol
M5M4257S-12
Min Max
Limits
M5M4257S-15
Min Max
M5M4257S-20
Min Max
Unit
ICR
Isu (A-CAS)
Ih (CAS-R)
Ihl AAS-R)
Read cycte time
Read setup time before CAS
Read hold time after CAS
.Read hold time after RAS-
lAC 230 260 330
I RCS
0
0
0
(Note'1)
I RCH
0
0
0
INote 11)
IRRH
20
20
25
ns
ns
ns
ns
Idls (CAS)
la (CAS)
la (RAS)
Output disable time
CAS access time
RAS access time
INote12)
INote 13)
(Note 14)
IOFF
ICAC
I AAC
0 35
60
120
0 40
75
150
0 50
100
200
ns
ns
ns
Note 11
12
13:
14
Either th (RAS-R) or th (CAS-R)~ must be satisfied for a read cycle.
tdi5 (CAS)maX defines the time at which the output achieves the open circuit condition and is not reference to VOH or VOL
This is the value when td (RAS-CAS)~ td (RAS- CAS)max. Test conditions; Load'" 2TTl, CL = 100pF
This is the value when td lRAS-CAS)< td (RAS-CAS)max. When td (RAS-CAS)~ td (RAS-CAS)max. ta (RAS) will increase by the amount that
td (RAS-CAS) exceeds the value shown. Test conditions; Load = 2TTL. 'C L = 100pF
Write Cycle
Symbol
Parameter
Icw
Isu (W-CAS)
Ih (CAS-W)
Ih (RAS-W)
Ih (W-RAS)
Ih (W-CAS)
tW(W)
Isu (O-CAS)
Ih (CAS-D)
Ih IAAS-O)
Write cycle time
Write setup time before CAS
Write hold time after CAS
Write hold time after RAS
RAS hold time after write
CAS hold time after write
Write pulse width
Data-in setup time before CAS
Data-in hold time after CAS
Data-in hold time after RAS
(Note 17)
Alternative
Symbol
I RC
I wcs
IWCH
IWCR
IAWL
ICWL
Iwp
los
IOH
IOHR
Limits
M5M4257S-12 M5M4257S-15 M5M4257S-20
Min Max Min Max Min Max
230 260 330
-5 -10 -10
40 45 55
100 120 155
40 45 55
40 45 55
40 45 55
0 00
30 35 40
90 110 140
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
• MITSUBISHI
"ELECTRIC
2-129
5 Page 
MITSUBISHI LSls
M5M4257S-12, -15, -20
262 144-BIT (262 144-WORD BY 1-BIT) DYNAMIC RAM
CAS before RAS Refresh Cycle INote 221
READ CYCLE
REFRESH CYCLE
tCR
RAS
V'H-
V'L-
twCRASLI
CAS
V'H-
VIL-
REF RESH CYCLE
tCR
READ OR WRITE
CYCLE
Ao-Aa
V'H-
V'L-
VOH-
Q ~------------------------~~-----HIGH IMPEDANCE STATE----------------------
VOL - ______- {
Note 22: W, 0 = don't care
TYPICAL CHARACTERISTICS
NORMALIZED ACCESS TIME
VS. SUPPLY VOLTAGE
1.3
;;;
<l
[(
1.2
~
:'>"
f=
1.1
eenn
'"uU 1.0
<l
0
'r":! 0.9
-.J
<l
:>
a: 0.8
0z
\ Ta~25'C
f\
\
,
~
~
.......
...........
0.7
4.0 5.0 6.0
NORMALIZED ACCESS TIME
VS. AMBIENT TEMPERATURE
1.3
iii
:::<l
1.2
~
:'>"
f=
1.1
eenn
u'U" 1.0
<l
0
r':"! 0.9
<l.
:>
a: 0.8
0z
vce~5.0)
1./
/V
,/
/"
V
'"
20 40 60 80 100
SUPPLY VOLTAGE Vee (V)
AMBIENT TEMPERATURE Ta ("C)
ACCESS TIME VS. LOAD
CAPACITANCE
25 VC~~4.5J
'"c 20 I--Ta~25'C
;;;
<l
[(
15
~
<l 10
:'>"
f=
eenn
U'"
U
<l
V
./
'"
VV
V
-5
100 200 300 400 500 600
LOAD CAPACITANCE CL (pF)
NIBBLE MODE ACCESS TIME
VS. SUPPLY VOLTAGE
iii 1.6
<{
z"
,
Ta~25A~ 1.4
:U:;J:
i= 1.2
(/J
(/J
UJ
uU
<l
1.0
UJ
-'
z''"" 0.8
'" ...............
r--......
f'
0
UJ
:N::; 0.6
:<:;:l
a:
0z 0.4
4.0
5.0
6.0
SUPPLY VOLTAGE Vce (V)
• MITSUBISHI
"'ELECTRIC
2-135
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet M5M4257S-20.PDF ] | |
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