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PDF M5M4257P-20 Data sheet ( Hoja de datos )
| Número de pieza | M5M4257P-20 | |
| Descripción | 256K-Bit DRAM | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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MITSUBISHI LSls
M5M4257P-12, -15, -20
262 144·BIT (262 144·WORD BY I.BIT) DYNAMIC RAM
DESCRIPTION
This is a family of 262 144-word by 1-bit dynamic RAMs,
fabricated with the high performance N-channel silicon gate
MOS process, and is ideal for large-capacity memory
systems where high speed, low power dissipation, and low
costs are essential. The use of double-layer polysi licon
process combined with silicide technology and a single-
transistor dynamic storage cell provide high circuit density
at reduced costs, and the use of dynamic circuitry including
sense amplifiers assures low power dissipation. Multiplexed
address inputs permit both a reduction in pins to the stand-
ard 16-pin package configuration and an increase in system
densities. In addition to the RAS only refresh mode, the
Hidden refresh mode and CAS before RAS refresh mode
are available.
FEATURES
Type name
Access time
(max)
(ns)
Cycle time
(min)
(ns)
Power dissipation
(typ)
(mW)
M5M4257P-12
120
230
260
M5M4257P -15
150
260
230
M5M4257P -20
200
330
190
• Standard 16-pm package
• Single 5V±10% supply
• Low standby power dissipation: 25mW (max)
• Low operating power dissipation:
M5M4257P-12 ........... 360mW (max)
M5M4257P-15 ........... 330mW (max)
M5M4257P-20 ........... 275mW (max)
• Unlatched output enables two-dimensional chip selec-
tion
BLOCK DIAGRAM
PIN CONFIGURATION (TOP VIEW)
ADDRESS INPUT As -+ I
DATA INPUT
WRITE
CONTROL INPUT
ROW ADDR ESS RA S -+ 4
STROBE INPUT
ADDRESS
INPUTS
(5V) Vee
Vss (OV)
15.- CAS ~~~g~~ I~~S~ESS
DATA OUTPUT
ADDRESS
INPUTS
Outline 16P4
• Early-write operation gives common I/O capability
• Read-modify-write, RAS-only-refresh, Nibble-mode
capabilities. (Pin 1 is used for nibble mode)
• CAS before RAS refresh mode capability
• All input terminals have low input capacitance and are
directly TTL-compatible
• Output is three-state and directly TTL-compatible
• 256 refresh cycles every 4ms. Pin 1 is not needed for
refresh.
• CAS controlled output allows hidden refresh
APPLICATION
• Main memory unit for computers
• Microcomputer memory
DATA INPUT
WRITE CONTROL
INPUT
D 2 r-------------------------------------------------,
w
INPUT
LATCH
I
~VCC<5V)
,
ADDRESS
INPUTS
1'""W'A2
32K
MEMORY
ARRAY
cr:
w
0
u0
w
32K
MEMORY
ARRAY
32K
MEMORY
ARRAY
cr:
CD
0
u0
CD
32K
MEMORY
ARRAY
IwI
0
u0w
0
0
0
W
-..J
A3
tIl
tIl
Z
A4
COLUMN
DECODER
l-
S
A5
U
II
U
A6
32K
MEMORY
ARRAY
S
0cr:
32K
MEMORY
ARRAY
32K
MEMORY
ARRAY
S
0cr:
32K
MEMORY
ARRAY
-..J
0
II
Iz-
u0
I
_ J~
L---L------
• MITSUBISHI
"'ELECTRIC
2-95
1 page  
MITSUBISHI LSls
M5M4257P-12, -15, -20
262 144-BIT (262 144-WORD BY 1-BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh, and Nibble-Mode Cycle)
(Ta = 0 ~ 70°C, Vee =SV 1: 10%, Vss =QV. unless otherwise noted, See notes 5, 6 and 7)
Symbol
Parameter
tCRF
I W(RASH)
IW(RASLl
IW(CASLl
I W(CASH)
Ih (RAS-CAS)
Ih (CAS-RAS)
Id (CAS-RAS)
~(RAS-CAS)
Isu (RA-RAS)
Isu (CA-CAS)
Ih (RAS-RA)
Ih (CAS-CA)
th (RAS-CA)
I THL
I TLH
Refresh cycle time
RAS high pulse width
RAS low pulse width
CAS low pulse width
LAS high pulse width
CAS hold time after RAS
RAS hold time after CAS
Delay time, CAS to RAS
Delay time. RAS to CAS
Row address setup time before RAS
Column address setup lime before CAS
Row address hold time after FfA""S
Column address hold time after CAS
Column address hold time after AAS
Transition time
INote81
INote 91
INote 101
Alternative
Symbol
IREF
IRP
I RAS
ICAS
ICPN
ICSH
I RSH
I CAP
I RCD
I ASR
IASC
I RAH
ICAH
IAR
tr
M5M4257P-12
Min Max
4
100
120 10000
60
30
120
60
30
20 60
0
-5
15
20
80
Limits
M5M4257P-15
Min Max
4
100
150 10000
75
35
150
75
30
25 75
0
-5
20
25
100
M5M4257P-20
Min Max
4
120
200 10000
100
40
200
100
40
30 100
0
-5
25
35
135
3 50 3 50 3 50
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 5
6
9
10
An initial pause of 500,us is required after power-up fo!lowed by any eight RAS or RAS/CAS cycles before proper device operation is achieved.
The switching characteristics are defined as t THL = t TLH = Sns.
Reference levels of input signals are VIH min. and VI L max. Reference levels for transition time are also between VIH and VI L.
Except for nibble-mode.
td (RAS~CAS) requirement is applicable for all RAS/CAS cycles.
Operation within the td (RAS-CAS) max limit insures that ta (RAS) max can be met. td (RAS-CAS)maX is specified reference point only.if
td (RAS-CAS) is greater than the specified td (RAS-CAS) max limit, then access time is controlled exclusively by ta (CAS).
= + +td (RAS-CAs)mm t h (RAS-RA)mm 2t THL (t TLH) t 5U(CA-CAS)mln.
SWITCHING CHARACTERISTICS (Ta =0-70'C, Vcc=5V ± 10%, VSS=OV, unless otherwise noted)
Read Cycle
Symbol
leR
Isu (R-CAS)
Ih (CAS-R)
Ih (RAS-R)
Idls (CAS)
la (CAS)
la (RAS)
Parameter
Read cycle time
Read setup time before CAS
Read hold time after CAS
Read hold time after AAS
Output disable time
CAS access time
RAS access time
(Note 11)
INote 11)
INote121
INote 131
(Note 14)
Alternative
Symbol
IRC
IRCS
I RCH
tRRH
IOFF
tCAC
I RAC
limits
M5M4257P-12 M5M4257P-15 M5M4257Fo-20
Min Max Min Max Min Max
230 260 330
000
000
20 20 25
0 35
0 40
0 50
60 75 100
120 150 200
Unit
ns
ns
ns
ns
ns
ns
ns
Note 11
12
13
14
Either th (RAS-A) or th (CAS-A) must be satisfied for a read cycle.
td IS (CAS)ma x defines the time at which the output achieves the open circuit condition and is not reference to VOH or VOL
This is the value when td (RAS-CAS)~ t d (RAS-CAs)max. Test conditions, Load = 2TTL. CL = 100pF
This is the value when td (RAS-CAS)< td (RAS- CAS)max. When td (RAS·CAS)~ td (RAS-CAS)max. t a (RAS) will increase by the amount that
td (AAS-CAS) exceeds the value shown. Test conditions; Load = 2TTL CL = 100pF
Write Cycle
Symbol
Parameter
tew
Isu (W-CAS)
Ih (CAS-W)
Ih (RAS-W)
Ih (W-RAS)
Ih IW-CAS)
Iw(w)
Isu (D-CAS)
Ih (CAS-D)
Ih (RAS-D)
Write cycle time
Write setup time before CAS
Write hold time after CAS
Write hold time after RAS
~hold time after write
CAS hold time after write
Write pulse width
Data-in setup time before ("AS
r nData-in hold time after
Data-in hold time after RAS
(Note 17)
Alternative
Symbol
I RC
IwCS
IWCH
IWCR
I RWL
I CWL
Iwp
IDS
IDH
I DHR
Limits
M5M4257P-12 M5M4257P-15 M5M4257P-20
Min Max Min Max Min Max
230 260 330
-10
-10
-10
40 45 55
100 120 155
40 45 55
40 45 55
40 45 55
000
30 35 40
90 110 140
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
• MITSUBISHI
. . . . . . ELECTRIC
2-99
5 Page 
MITSUBISHI LSls
M5M4257P-12, -15, -20
262 i44-BIT (262 i44-WORD BY i-BIT) DYNAMIC RAM
CAS before RAS Refresh Cycle I Note 221
READ CYCLE
REFRESH CYCLE
tCA
RAS
VIH-
VIL -
tW(AASL)
CAS
VIH-
VIL -
REFRESH CYCLE
tCA
READ OR WRITE
CYCLE
Ao-As
VIH-
VIL -
VOH-
Q
}-------------------------~~-----HIGH IMPEDANCE STATE----------------------
VOL- _ _ _ _- (
Note 22: IN, D = don't care.
TYPICAL CHARACTERISTICS
NORMALIZED ACCESS TIME
VS. SUPPLY VOLTAGE
,1.3
u;
Ta~25'C
'":s 1.2
.'3
"w
\:;> 1.1 --
f-
U'>
U'>
~W
uu 1.0
q
0
~
w
':'
0.9
-q"
..........
.............
:;>
a:
0z
0.8
i0.7
4.0
I
5.0 6.0
NORMALIZED ACCESS TIME
VS. AMBIENT TEMPERATURE
1.3
;;;
:'"s 1.2
.'3
w
:;>
f=
1.1
U'>
Uw'>
uu 1.0
q
0
w
N
0.9
~
q
:;>
a: 0.8
0z
I .1
Vcc=5.0V
/
./
.i'
./
V
/'
0.7_ 20 0
20 40 60 80 100
SUPPLY VOLTAGE Vcc (V)
AMBIENT TEMPERATURE Ta (,C)
ACCESS TIME VS. LOAD
CAPACITANCE
5 II.
Vcc=4.5V
20 t--Ta =25'C
15
l;-
V10 V
o
VV
'"
-5
100 200 300 400 500 600
LOAD CAPACITANCE CL (pF)
NIBBLE MODE ACCESS TIME
VS. SUPPLY VOLTAGE
;;; 1.6
2'"
z
Ta=25~.'3 1.4
UJ
2
i= 1.2
()')
()')
w
Uu
q
1.0
w
cc-oo"
Z
0.8
'"i"-........!'-......
I'
w0
N
::J 0.6
<t
c2r
0z 0.4
4.0
5.0
6.0
SUPPLY VOLTAGE Vcc (V)
• MITSUBISHI
...... ELECTRIC
2-105
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet M5M4257P-20.PDF ] | |
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