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PDF M5M5118P-15 Data sheet ( Hoja de datos )
| Número de pieza | M5M5118P-15 | |
| Descripción | 16K-Bit CMOS Static RAM | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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MITSUBISHI LSls
MSMSI18P, -15
16384-B1T (2048-WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5118P series of 2048-word by 8-bit asynchronous
silicon gate CMOS static RAM operates on a single 5V
power supply and is designed for easy use in applications
requiring battery back - up_
Two chip select inputs, Sl and S2, are available to pro-
vide the minimum standby current with battery back-up_
The series is packaged in a standard 24-pin plastic OIL
package.
FEATURES
Type name
M5M5118P-15
M5M5118P
Access time
(max)
150ns
200ns
Current consumption
Active
(max)
Stand-by
(max)
50mA
15,uA
PIN CONFIGURATION (TOP VIEW)
A7 - 1
ADDRESS
INPUTS
A3
A,
A,
Ao
DATA DO,
1INPUTS/ DO,
OUTPUTS D03
(OV) GND
Vee (SV)
I23 ~ As
I22 ~ A, ADDRESS INPUTS
WRITE CONTROL
INPUT
20 ~ S, CHIP SELECT INPUT
" ~ AlO ADDRESS INPUT
18 ~ S, CHIP SELECT INPUT
DATA
INPUTS/
OUTPUTS
• Single 5V power supply.
• External clock and refresh operation not required.
• Data can be held with 2V supply voltage_
• All inputs and outputs are directly TTL compatible.
• All outputs are 3-state with OR-tie capability.
• Easy expansion of memory capacity with chip select
signal.
• Common input/output for data pins
APPLICATIONS
Battery drive, small-capacity memory units with battery
back-up
Outline 24 P4
FUNCTION
The M5M5118P series has a 2048-word by 8-bit configura-
tion. It operates on a single 5V supply and its inputs/
outputs are directly TTL compatible. Its completely static
circuitry obviates the need for external clock and refresh
operations and makes it very easy to use. The data of the
DO pin are written when the address is designated by
address signals Ao ~ AlO , the S; and S2 signals turn low-
level, and the IN signal is set low.
When for the reading operation the W signal is set high,
the Sl and S2 signals are set low, pin DO is set to the output
BLOCK DIAGRAM
A,
As
A,
A3
ADDRESS INPUTS
acu: 2048-WORD X 8-BIT
0
1.
0
~
128
RAM
x0 (128 ROWS
S
0
a: 128 COLUMNSI
DATA
INPUTS/OUTPUTS
WRITE CONTROL INPUT
I~CHIP SELECT INPUTS
18
8, ~~~~__________________________~
-'--------- - - - - - - - - - - - - - - - - - - - - - - ------~
• MITSUBISHI
"ELECTRIC
4-23
1 page  
MITSUBISHI LSls
M5M5118P, -15
16384-BIT (2048-WORD BY 8-Blt) CMOS STATIC RAM
Write cycle (8 control)
lew
tsu (s)
w
DO,-DOg
(DATA IN)
DO,-DOg
(DATA OUT)
Note 4: Test conditions
Input pulse level: 0.4 ""-' 2.4V
Input pulse risetime and falltime
Load: lTTL. CL = 100pF
Reference level: 1.5V
10ns
Note 5 Hatching indicates the don't care inputs.
6 Writing is performed while Sand Ware in the low-level
overlap period.
The output is kept in the high-impedance state when IN
.fails simultaneously with, or before, the S fall.
8: An reverse-phase signal should not be supplied when pin
DQ is in the output mode.
POWER-DOWN CHARACTERISTICS
Vee
• MITSUBISHI
.... ELECTRIC
4-27
5 Page | ||
| Páginas | Total 5 Páginas | |
| PDF Descargar | [ Datasheet M5M5118P-15.PDF ] | |
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