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PDF M5K4164AND-12 Data sheet ( Hoja de datos )
| Número de pieza | M5K4164AND-12 | |
| Descripción | 64K-Bit DRAM | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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MITSUBISHI LSls
MsK4164AND-12, -15
65 536-BIT (65 536-WORD BY i-BIT) DYNAMIC RAM
DESCRIPTION
This is a family of 65 536-word by 1-bit dynamic RAMs,
fabricated with the high performance N-channel silicongate
MOS process, and is ideal for large-capacity memory
systems where high speed, low power dissipation, and low
costs are essential. The use of double-layer polysil icon
process technology and a single-transistor dynamic storage
cell privide high circuit density at reduced costs, and the
use of dynamic circuitry including sense amplifiers assures
low power dissipation. Multiplexed address inputs permit
both a reduction in pins to the 18-pin chip carrier package
configuration and an increase in system densities. The
M5K4164AND operates on a 5V power supply using the
on-chip substrate bias generator.
FEATURES
• Performance ranges
Type name
M5K4164AND-12
M5K4164AND-15
Access time
(max~
(ns)
120
150
Cycle time
(min)
(ns)
220
260
Power dissipation
(typ)
(mW)
175
150
• Single 5V±10%supply
• Low standby power dissipation:
22mW (max)
• Low operating power dissipation:
M5K4164AND-12 275mW (max)
M5K4164AND-15 250mW (max)
• Unlatched output enables two-dimensional chip selec-
tion and extended page boundary
• Early-write operation gives common I/O capability
• Read-modify-write, RAS-only refresh, and page-mode
capabilities
PIN CONFIGURATION (TOP VIEW)
o NC Vss CAS
NC ~~JM5K4164ANDC~~ NC
AO -:6:J
m A3
A2 :,:~
[I? A4
:..8-:, :r-9": :r1-0": :,.,-,:,
At Vee A, As
Outline 1800
• All input terminals have low input capaciatance and are
directly TTL-compatible
• Output is three-state and directly TTL-compatible
• 128 refresh cycles every 2ms
(16K dynamic RAMs M5K4116P, S compatible)
• CAS controlled output allows hidden refresh
• Output data can be held infinitely by CAS
APPLICATION
• Main memory unit for computers
BLOCK DIAGRAM
DATA INPUT
WRITE CONTROL INPUT
W
COL~~RNO:f?~~0f CAS
ROW ADDRESS
STROBE INPUT
ADDRESS INPUTS
MEMORY CELL
(64 ROWS X 256 COLUMNS)
SENSE REFRESH AMPLIFIER
MEMORY CELL
(64 ROWS X 256 COLUMNS)
COLUMN DECODER
MEMORY CELL
(64 ROWS X 256 COLUMNS)
SENSE REFRESH AMPLIFIER
(64 ROMWESMXOR2Y56CCEOLLUMNS)
COLUMN DECODER
....
:5
ua:
U
o-'
.uoaz..:.
g
Vee ('V)
Vss (OV)
J'
• MITSUBISHI
"ELECTRIC
2-55
1 page  
MITSUBISHI LSls
MsK4164AND-12, -15
65 536-BIT (65 536-WORD BY I-BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh, and Page-Mode Cycle)
(Ta=O --10·C. Vcc=sv -t 10%. Vss=OV, unless otherwise noted, See notes 5,6and 7)
Symbol
Parameter
leRF
I W(RASH)
I W(RASL)
I W(CASL)
I W(CASH)
I h (RAS-CAS)
I h (CAS-RAS)
Id (CAS-RAS)
Id(RAS-CAS)
I SU(RA-RAS)
I SU (CA-CAS)
Ih(RAS-RA)
I h (CAS-CA)
Ih(RAS-CA)
I THL
ITLH
Refresh cycle time
RAS high pulse width
RAS low pulse width
CAS low pulse width
CAS high pulse width
CAS hold time after RAS
RAS hold time after CAS
Delay time, CAS to RAS
Delay time, RAS to CAS
Row address setup time before RAS
Column address setup time before CAS
Row address hold time after RAS
Column address hold time after CAS
Column address hold time after RAS
Transition time
(Note 8)
INote 9)
(NatelO)
Alternative
Symbol
t REF
IRP
I RAS
ICAS
ICPN
ICSH
I RSH
ICRP
I RCo
I ASR
IASC
IRAH
I CAH
I AR
IT
M5K4164ANO-12
Limits
Min Max
2
90
120 10000
60 00
30
120
60
-20
25 60
0
0
15
20
90
3 35
M5K4164ANO-15
Limits
Min Max
2
100
150 10000
75 00
35
150
75
-20
30 75
0
0
20
25
95
3 50
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 5.
6
9
10.
An initial pause of 5001-'5 is required after power·up followed by any eight RAS or RAS/CAS cycles before proper device operation is achieved
= =The switching characteristics are defined as t THL t TLH Sns.
Reference levels of input signals are V 1H min, and VI L max. Reference levels for transition time are also between VIH and V, L.
Except for page·mode.
tdICAS.RAS) requirement is only applicable for RAS/CAS cycles preceeded by a CAS only cycle (i.e., For systems where CAS has not been decoded with RAS.)
Operation within the td (RAS.CAS) max limit insures that ta (RAS) max can be met. td (RAS-CAS)maX is specified reference point onlY,if
td (RAS-CAS) is greater than the specified td (RAS-CAS) max limit, then access time is controlled exclusively by taICAS)'
=td (RAS-CAs)mln th (RAS-RA)mln + 2t THL(t TLH) + t SU(CA·CAS)mm.
SWITCHING CHARACTERISTICS (Ta=0-70'C, Vcc=5V±10%, VSs=OV, unlessOtherw;senoted)
Read Cycle
Symbol
te R
Isu (R-CAS)
Ih (CAS-R)
thIRAS-R}
Id,s (CAS)
la (CAS)
la (RAS)
Parameter
Read cycle time
Read setup time before CAS
Read hold time after CAS
Read hold time after RAS
Output disable time
CAS access time
RAS access time
INote 111
(Note 111
INote 12)
(Note 13)
(Note 14)
Alternative
Symbol
I RC
I RCS
I RCH
IRRH
IOFF
ICAC
I RAC
M5K4164ANO-12
Limits
Min Max
220
0
0
10
0 35
60
120
M5K4164ANO-15
Limits
Min Max
260
0
0
20
0 40
75
150
Unit
ns
ns
ns
ns
ns
ns
ns
Note 11
Note 12.
Note 13.
Note 14.
Either th (RAS-R) Of th (CAS-R) must be satisfied for a read cycle.
tdls (CAS)maX defines the time at which the output achieves the open circuit condition and is not reference to VOH or VOL
This is the value when td (RAS-CAS)~td (RAS-CAS)max. Test conditions; Load'" 2T TL, CL = 100pF
This is the value when td (RAS-CAS)< td (AAS-CAS)maX, When td (AAS-CAS)~td (RAS-CAS)maX, ta (RAS) will increase by the amount that
td (AAS-CAs)exceeds the value shown. Test conditions; Load = 2T TL. CL = lOOpF
Write Cycle
Symbol
Parameter
leW
Isu (W-CAS)
Ih (CAS-W)
Ih (RAS-W)
Ih (W-RAS)
Ih (W-CAS)
Iw(w)
Isu (D-CAS)
Ih (CAS-D)
Ih (RAS-o)
Write cycle ti me
Write setup time before CAS
Write ho4d time after CAS
Write hold time after RAS
RAS hold time after write
CAS hold time after write
Write pulse width
Data-in setup time before CAS
Data-in hold time after CAS
Data-in hold time after RAS
(Note 17)
Alternative
Symbol
t RC
IwCS
tWCH
IWCR
I RWL
ICWL
Iwp
lOS
10H
10HR
M5K4164ANO-12
Limits
Min Max
220
5
40
90
40
40
40
0
40
90
M5K4164ANO-15
limits
Min Max
260
5
45
95
45
45
45
0
45
95
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
• MITSUBISHI
;"ELECTRIC
2-59
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