|
|
PDF M5K4164AP-15 Data sheet ( Hoja de datos )
| Número de pieza | M5K4164AP-15 | |
| Descripción | 64K-Bit DRAM | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de M5K4164AP-15 (archivo pdf) en la parte inferior de esta página. Total 11 Páginas | ||
|
No Preview Available !
MITSUBISHI LSI.
M5K4164AP-12, -15
65 536·BIT (65 536·WORD BY 1.BIT) DYNAMIC RAM
DESCRIPTION
This is a family of 65 536-word by l-bit dynamic RAMs,
fabricated with the high performance N-channel silicongate
MOS process, and is ideal for large-capacity memory
systems where high speed, low power dissipation, and low
costs are essential. The use of double-layer polysilicon
process technology and a single-transistor dynamic storage
cell privide high circuit density at reduced costs, and the
use of dynamic circuitry including sense amplifiers assures
low power dissipation_ Multiplexed address inputs permit
both a reduction in pins to the standard 16-pin package
configuration and an increase in system densities_ The
M5K4164AP operates on a 5V power supply using the
on-chip substrate bias generator_
PIN CONFIGURATION (TOP VIEW)
REFRESH INPUT REF
DATA INPUT
WRITE
CONTROL INPUT
ROW ADDRESS
STROBE INPUT
ADDRESS INPUTS
(WI Vee
Vss (OV)
15 ... CAS ~?~g~EN 1~~8fESS
I• ... Q DATA OUTPUT
ADDRESS INPUTS
FEATURES
• High speed
Type name
M5K4164AP-12
M5K4164AP-15
Access lime
~max I
(nsl
120
150
Cycle time
(min)
(ns)
220
260
Power diSSipation
(typ)
(mW)
175
150
• Single 5V±10%-supply
• Low standby power dissipation:
22mW (max)
• Low operating power dissipation: 300mW (max)
• Unlatched output enables two-dimensional chip selec-
tion and extended page boundary
• Early-write operation gives common 1/0 capability
• Read-modify-write, RAS-only refresh, and page-mode
capabilities
• All input terminals have low input capaciatance and are
directly TTL-compatible
Outline 16P4
• Output is three-state and directly TTL-compatible
• 128 refresh cycles every 2ms
(16K dynamic RAMs M5K4116P, S compatible)
• CAS controlled output allows hidden refresh
• Output data can be held infinitely by CAS
• Pin 1 controls automatic- and Self-refresh mode_
• Interchangeable with Fujitsu MB8265A and Motorola's
MCM6664 in pin configuration
APPLICATION
• Main memory unit for computers
BLOCK DIAGRAM
DATA INPUT
WRITE CONTROL INPUT
COLLUMN ADDRESS
STROBE INPUT
ROW ADDRESS
STROBE INPUT
ADDRESS INPUTS
COLUMN DECDDER
MEMORY CELL
164 ROWS X 256 COLLUMNS
SENSE REFRESH AMPLIFIER
MEMORY CELL
(64 ROWS x 256 COLUMNSI
COLUMN DECODER
MEMORY CELL
(64 ROWS x 256 COLUMNSI
SENSE REFRESH AMPLIFIER
(64 ROMWESMXOR2Y56CCEOLLLUMNSI
COLUMN DECODER
Vee (5V)
Vss (OV)
f-
12 14 Q DATA OUTPUT
f-
JoOJ
• . MITSUBISHI
;"ELECTRIC
2-3
1 page  
MITSUBISHI LSls
MsK4164AP-12, -IS
65 536·BIT (65 536·WORD BY t.BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh, and Page-Mode Cycle)
(T a = 0 -70°C. Vee = 5 V ± 10%, v 55 = 0 V. unless otherwise noted, See notes 5, 6 and 7)
Symbol
Parameter
Alternative
Symbol
M5K4164AP-12
Limits
Min Max
M5K4164AP-15
Limits
Min Max
Unit
leAF
Refresh cycle time
I REF
2
2 ms
t W (RASH)
RAS high pulse width
I RP
90
100 ns
t W(RASL)
RAS low pulse width
I AAS 120 10000
150 10000 ns
t W(CASLl
CAS low pulse width
ICAS
60
co
75 co ns
t W (CASH)
CAS high pulse width
INoH' 8~
I CPN
30
35 ns
t h (RAS·CAS)
CAS hold time after RAS
I CSH
120
150 ns
t h (CAS· RAS)
RAS hold time after CAS
I ASH
60
75 ns
Id (CAS AAS) Delay time, CAS to RAS
(Note 9)
I CAP
20
-20
ns
t d (RAS-CAS)
Delay time, RAS to CAS
(Note 10)
I ACD
25
60 30
75 ns
t su (RA- AAS)
Row address setup time before RAS
I ASR
0
0 ns
t su (eA-CAS)
Column address setup time before CAS
tAse
0
0 ns
t h (RAS-RA)
Row address hold ti me after RAS
t RAH
15
20 ns
I h (CAS"CA)
Column address hold time after CAS
I CAH
20
25 ns
th(RAS-CA)
Column address hold time after RAS
I AR 90
95 ns
t THL
t TLH
Note
Transition time
IT 3 35 3 35
- -An initial pause of 500/1s IS required after power-up followed by any eight -RAS or RAS/CAS cycles before proper deVice operation is achieved
= =The switching characteristics are defined as t THL t TLH 5ns.
ns
7 Reference levels of input signals are VIH min and VIL max. Reference levels for transition time are also between VIH and VIL.
8 Except for page-mode
n.9: td (CAS-RAS) requirement is only applicable for RAS/CAS cycles preceeded by a CAS only cycle e For systems where CAS has not been decoded with RAS _)
10' Operation within the td eRAS-CAS) max limit insures that ta (RAS) max can be met. td (RAS-CAS) max is specified reference point only:if
td (RAS-CAS) IS greater than the specified td (RAS-CAS) max limit, then access time IS controlled exclUSively by ta (CAS).
Id(RAS"CAS)mln = th (RAS"RA)min + 21 THL( tTLH) + tsu (CA"CAS)mln.
SWITCHING CHARACTERISTICS (Ta=O~70·C. Vcc=5V±10%. VSs=OV. unless otherw'5enotedl
Read Cycle
Symbol
lOR
Isu (A"CAS)
Ih (CAS"A)
thl RAS-R)
Idis (CAS)
la (CAS)
la (RAS)
Parameter
Read cycle time
Read setup time before CAS
Read hold time after CAS
Read hold time after RAS
Output disable tir~Je
CAS access time
RAS access time
Alternative
Symbol
(Note 11 \
(Note 111
(Note 121
(Note 131
(Note 141
I RC
lACS
I RCH
I RRH
IOFF
t CAC
t AAC
M5K4164AP-12
Limits
Min Max
220
0
0
10
0 35
60
120
M5K4164AP-15
Limits
Min Max
260
0
0
20
0 40
75
150
Unit
ns
ns
ns
ns
ns
ns
ns
Note 11;
Note 12:
Note 13:
Note 14'
Either th (AAS-R) or th (CAS-R) must be satisfied for a read cycle
td is (C AS) max defines the time at which the output achieves the open circuit condition and is not reference to VOH or VOL
This is the value when td (RAS-CAS) ~ td (RAS~CAS) max. Test conditions: Load=2T TL, CL= 100pF
<This is the value when td (RAS-CAS) td (RAS-CAS) max. When td (RAS.CAS) ~ td (RAS-CAS) max. ta (RAS) will increase by the amount that
td (RAS-CAS) exceeds the value shown Test conditions; Load =2T TL, CL= 100pF
Write Cycle
Symbol
lew
tsu (W'CAS)
Ih (CAS"W)
Ih (AAS"W)
Ih (W.AAS)
th (W"CAS)
IW(WI
Isu CO"CAS)
Ih (CAS"O)
Ih (AAS"D)
Parameter
Write cycle time
Write setup time before CAS
Write hold time after CAS
Write hold time after RAS
RAS hold time after write
CAS hold time after writ.e
Write pulse width
Data-in setup time before CAS
Data-in hold time after CAS
Data-in hold time after RAS
Alternative
Symbol
(Note 17)
I RC
I WCS
IWCH
IWCR
I AWL
ICWL
Iwp
IDS
IOH
IOHR
M5K4164AP-12
Limits
Min Max
220
-5
40
90
40
40
40
0
40
90
M5K4164AP-15
Limits
Min Max
260
-10
45
95
45
45
45
0
45
95
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
• MITSUBISHI
"ELECTRIC
2-7
5 Page 
MITSUBI.SHI LSls
MSK4164AP.12, ·15
65 536-BIT (65 536-WORD BY 1-BIT) DYNAMIC RAM
Hidden Self-Refresh Cycle (Note 21)
READ CYCLE
Vi V,H
V,L
REF
V,H
V,L
td(RAS-REF)
ta(RAS)
Iw(REFL)
VOH
Q
VOL
DATA VALID
Note 21: If the pin 1 (REF) function is not used. pin 1 may be left open (not connect)
Hidden Refresh Cycle (Note 19)
READ CYCLE
teR
REFRESH CYCLE
leR
tW(AASL)
t w ( RASL)
td(CAS-RAS)
td (RAS-CAS)
Iw (RASH)
Ih (CAS-RAS)
tw (CASU
Id(REF-RAS)
Idls (CAS)
REFRESH CYCLE
leR
IW(RASL)
IW(CASH)
ISU(RA-RAS) th(RAS-RA)
ISU(RA-RAS)
V,H
Vi
V,L
VOH
Q
VOL
DATA VALID
• MITSUBISHI
.... ELECTRIC
tdls (CAS)
2-13
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet M5K4164AP-15.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| M5K4164AP-12 | 64K-Bit DRAM | Mitsubishi |
| M5K4164AP-15 | 64K-Bit DRAM | Mitsubishi |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |