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PDF XS1-L01A-LQ64 Data sheet ( Hoja de datos )

Número de pieza XS1-L01A-LQ64
Descripción MCU 32BIT 8KB OTP
Fabricantes Xmos 
Logotipo Xmos Logotipo



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No Preview Available ! XS1-L01A-LQ64 Hoja de datos, Descripción, Manual

XS1-L01A-LQ64 Datasheet
2012/10/15
XMOS © 2012, All Rights Reserved
Document Number: X1135,

1 page




XS1-L01A-LQ64 pdf
XS1-L01A-LQ64 Datasheet
4
3 Signal Description
Module
Power
PLL
JTAG
I/O
Signal
Function
Type
Active Properties
PU=Pull Up, PD=Pull Down, ST=Schmitt Trigger Input, OT=Output Tristate, S=Switchable
GND
RS=Required for SPI boot (§5.6), RU=Required for USB-enabled devices (§10)
Digital ground
GND
VDD
Digital tile power
PWR
VDDIO
Digital I/O power
PWR
PLL_AGND
Analog ground for PLL
PWR
PLL_AVDD
Analog PLL power
GND
RST_N
Global reset input
Input
Low
PU, ST
CLK PLL reference clock
Input
PD, ST
MODE[3:0]
Boot mode select
Input
PU, ST
TDI Test data input
Input
PU, ST
TDO
Test data output
Output —
PD, OT
TMS
Test mode select
Input
PU, ST
TRST_N
Test reset input
Input
Low
PU, ST
TCK
Test clock
Input
PU, ST
DEBUG_N
Multi-chip debug
I/O Low
X0D00
X0D01
X0D02
X0D03
X0D04
X0D05
X0D06
X0D07
X0D08
X0D09
X0D10
X0D11
X0D12
X0D13
X0D14
X0D15
X0D16
X0D17
X0D18
X0D19
X0D20
X0D21
X0D22
X0D23
X0D24
X0D25
X0D26
X0D27
X0D32
X0D33
X0D34
X0D35
X0D36
X0D37
X0D38
X0D39
P1A0
XXXXLLLLAAAA45352512obobobbo/5b P1B0
P4A0 P8A0 P16A0
P4A1 P8A1 P16A1
P4B0 P8A2 P16A2
XLA02bo/5b
P4B1 P8A3 P16A3
XLA02bi /5b
P4B2 P8A4 P16A4
XLA12bi /5b
P4B3 P8A5 P16A5
XXXLLLAAA253545ibibib
P4A2 P8A6 P16A6
P4A3 P8A7 P16A7
P1C0
P1D0
P32A20
P32A21
P32A22
P32A23
P32A24
P32A25
P32A26
P32A27
P1E0
XXXXLLLLBBBB45352512obobobbo/5b P1F0
P4C0 P8B0
P4C1 P8B1
P4D0 P8B2
P16A8 P32A28
P16A9 P32A29
P16A10
XLB02bo/5b
P4D1 P8B3 P16A11
XLB02bi /5b
P4D2 P8B4 P16A12
XLB12bi /5b
P4D3 P8B5 P16A13
XXXLLLBBB253545ibibib
P4C2 P8B6 P16A14 P32A30
P4C3 P8B7 P16A15 P32A31
P1G0
P1H0
P1I0
P1J0
P4E0 P8C0 P16B0
P4E1 P8C1 P16B1
P4E2 P8C6 P16B6
P4E3 P8C7 P16B7
P1K0
P1L0
P1M0
P8D0 P16B8
P1N0
P8D1 P16B9
P1O0
P8D2 P16B10
P1P0
P8D3 P16B11
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PDS, RS
PDS, RS
PDS, RU
PDS, RU
PDS, RU
PDS, RU
PDS, RU
PDS, RU
PDS, RU
PDS, RU
PDS, RS
PDS, RS
PDS, RU
PDS, RU
PDS, RU
PDS, RU
PDS, RU
PDS, RU
PDS, RU
PDS, RU
PDS, RU
PDS, RU
PDS, RU
PDS, RU
PDS
PDS
PDS, RU
PDS, RU
PDS, RU
PDS, RU
PDS
PDS
PDS
PDS, RU
PDS, RU
PDS, RU
X1135,

5 Page





XS1-L01A-LQ64 arduino
XS1-L01A-LQ64 Datasheet
10
· OTP Master and Sector Lock: Further access to the OTP is prevented by setting
the master lock. Locks can also be applied to each of the four OTP sectors
individually.
These security features provide a strong level of protection and are sufficient for
providing strong IP security.
5.8 SRAM
The xCORE Tile integrates a single 64 KB SRAM bank for both instructions and
data. All internal memory is 32 bits wide, and instructions are either 16-bit or
32-bit. Byte (8-bit), half-word (16-bit) or word (32-bit) accesses are supported and
are executed within one tile clock cycle. There is no dedicated external memory
interface, although data memory can be expanded through appropriate use of the
ports.
5.9 JTAG
The JTAG module can be used for loading programs, boundary scan testing, in-
circuit source-level debugging and programming the OTP memory.
BS TAP
CHIP TAP
TDI TDI TDO TDI TDO
TDO
Figure 5:
JTAG chain
structure
TCK
TMS
TRST_N
DEBUG_N
The JTAG chain structure is illustrated in Figure 5. Directly after reset, two TAP
controllers are present in the JTAG chain: the boundary scan TAP and the chip TAP.
The boundary scan TAP is a standard 1149.1 compliant TAP that can be used for
boundary scan of the I/O pins. The chip TAP provides access into the xCORE Tile,
switch and OTP for loading code and debugging.
The TRST_N pin must be asserted low during and after power up for 100 ns. If JTAG
is not required, the TRST_N pin can be tied to ground to hold the JTAG module in
reset.
The DEBUG_N pin is used to synchronize the debugging of multiple xCORE Tiles.
This pin can operate in both output and input mode. In output mode and when
configured to do so, DEBUG_N is driven low by the device when the processor hits
a debug break point. Prior to this point the pin will be tri-stated. In input mode
and when configured to do so, driving this pin low will put the xCORE Tile into
debug mode. Software can set the behavior of the xCORE Tile based on this pin.
X1135,

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