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PDF C8051F521 Data sheet ( Hoja de datos )

Número de pieza C8051F521
Descripción 8/4/2 kB ISP Flash MCU
Fabricantes Silicon Laboratories 
Logotipo Silicon Laboratories Logotipo



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No Preview Available ! C8051F521 Hoja de datos, Descripción, Manual

Analog Peripherals
- 12-Bit ADC
Programmable throughput up to 200 ksps
Up to 6/16 external inputs
Data dependent windowed interrupt generator
Built-in temperature sensor
- Comparator
Programmable hysteresis and response time
Configurable as wake-up or reset source
Low current
- POR/Brownout Detector
- Voltage Reference—1.5 and 2.2 V
(programmable)
On-Chip Debug
- On-chip debug circuitry facilitates full-speed, non-
intrusive in-system debug (No emulator required)
- Provides breakpoints, single stepping
- Inspect/modify memory and registers
- Complete development kit
Supply Voltage 2.0 to 5.25 V
- Built-in LDO regulator
High-Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
- Up to 25 MIPS throughput with
25 MHz system clock
- Expanded interrupt handler
C8051F52x/F53x
8/4/2 kB ISP Flash MCU Family
Memory
- 8/4/2 kB Flash; In-system byte programmable in
512 byte sectors
- 256 bytes internal data RAM
Digital Peripherals
- 16/6 port I/O; push-pull or open-drain, 5 V tolerant
- Hardware SPI™, and UART serial port
- LIN 2.1 Controller (Master and Slave capable); no
crystal required
- Three general purpose 16-bit counter/timers
- Programmable 16-bit counter/timer array with three
capture/compare modules, WDT
Clock Sources
- Internal oscillators: 24.5 MHz ±0.5% accuracy sup-
ports UART and LIN-Master operation
- External oscillator: Crystal, RC, C, or Clock
(1 or 2 pin modes)
- Can switch between clock sources on-the-fly
Packages
- 10-Pin DFN (3 x 3 mm)
- 20-pin QFN (4 x 4 mm)
- 20-pin TSSOP
Automotive Qualified
- Temperature Range: –40 to +125 °C
- Compliant to AEC-Q100
Rev. 1.4 4/12
ANALOG
PERIPHERALS
A 12-bit
M
U
200 ksps
X ADC
+
-
TEMP
SENSOR
VOLTAGE
COMPARATOR
VREF VREG
DIGITAL I/O
UART
SPI
PCA
Timer 0
Timer 1
Timer 2
Port 0
Port 1
LIN
24.5 MHz High Precision (±0.5%) Internal Oscillator
HIGH-SPEED CONTROLLER CORE
8/4/2 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
8051 CPU
(25 MIPS)
DEBUG
CIRCUITRY
256 B SRAM
POR WDT
Copyright © 2012 by Silicon Laboratories
C8051F52x/F53x

1 page




C8051F521 pdf
C8051F52x/F52xA/F53x/F53xA
14.2.2. External Crystal Example...................................................................... 139
14.2.3. External RC Example............................................................................ 141
14.2.4. External Capacitor Example.................................................................. 141
14.3. System Clock Selection................................................................................. 143
15. UART0 ................................................................................................................... 144
15.1. Enhanced Baud Rate Generation.................................................................. 145
15.2. Operational Modes ........................................................................................ 146
15.2.1. 8-Bit UART ............................................................................................ 146
15.2.2. 9-Bit UART ............................................................................................ 147
15.3. Multiprocessor Communications ................................................................... 148
16. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 151
16.1. Signal Descriptions........................................................................................ 152
16.1.1. Master Out, Slave In (MOSI)................................................................. 152
16.1.2. Master In, Slave Out (MISO)................................................................. 152
16.1.3. Serial Clock (SCK) ................................................................................ 152
16.1.4. Slave Select (NSS) ............................................................................... 152
16.2. SPI0 Master Mode Operation ........................................................................ 153
16.3. SPI0 Slave Mode Operation .......................................................................... 154
16.4. SPI0 Interrupt Sources .................................................................................. 155
16.5. Serial Clock Timing........................................................................................ 156
16.6. SPI Special Function Registers ..................................................................... 156
17. LIN (C8051F520/0A/3/3A/6/6A and C8051F530/0A/3/3A/6/6A) .......................... 164
17.1. Software Interface with the LIN Peripheral .................................................... 165
17.2. LIN Interface Setup and Operation................................................................ 165
17.2.1. Mode Definition ..................................................................................... 165
17.2.2. Baud Rate Options: Manual or Autobaud ............................................. 165
17.2.3. Baud Rate Calculations—Manual Mode ............................................... 165
17.2.4. Baud Rate Calculations—Automatic Mode ........................................... 168
17.3. LIN Master Mode Operation .......................................................................... 169
17.4. LIN Slave Mode Operation ............................................................................ 170
17.5. Sleep Mode and Wake-Up ............................................................................ 171
17.6. Error Detection and Handling ........................................................................ 171
17.7. LIN Registers................................................................................................. 172
17.7.1. LIN Direct Access SFR Registers Definition ......................................... 172
17.7.2. LIN Indirect Access SFR Registers Definition....................................... 174
18. Timers ................................................................................................................... 182
18.1. Timer 0 and Timer 1 ...................................................................................... 182
18.1.1. Mode 0: 13-bit Counter/Timer ............................................................... 182
18.1.2. Mode 1: 16-bit Counter/Timer ............................................................... 184
18.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload..................................... 184
18.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................ 185
18.2. Timer 2 .......................................................................................................... 190
18.2.1. 16-bit Timer with Auto-Reload............................................................... 190
18.2.2. 8-bit Timers with Auto-Reload............................................................... 191
18.2.3. External Capture Mode ......................................................................... 192
Rev. 1.4
5

5 Page





C8051F521 arduino
C8051F52x/F52xA/F53x/F53xA
SFR Definition 13.13. P0SKIP: Port0 Skip .................................................................. 134
SFR Definition 13.14. P1MAT: Port1 Match ............................................................... 134
SFR Definition 13.15. P1MASK: Port1 Mask .............................................................. 134
SFR Definition 14.1. OSCICN: Internal Oscillator Control .......................................... 137
SFR Definition 14.2. OSCICL: Internal Oscillator Calibration ..................................... 138
SFR Definition 14.3. OSCIFIN: Internal Fine Oscillator Calibration ............................ 138
SFR Definition 14.4. OSCXCN: External Oscillator Control ........................................ 142
SFR Definition 14.5. CLKSEL: Clock Select ............................................................... 143
SFR Definition 15.1. SCON0: Serial Port 0 Control .................................................... 149
SFR Definition 15.2. SBUF0: Serial (UART0) Port Data Buffer .................................. 150
SFR Definition 16.1. SPI0CFG: SPI0 Configuration ................................................... 157
SFR Definition 16.2. SPI0CN: SPI0 Control ............................................................... 158
SFR Definition 16.3. SPI0CKR: SPI0 Clock Rate ....................................................... 159
SFR Definition 16.4. SPI0DAT: SPI0 Data ................................................................. 160
SFR Definition 17.1. LINADDR: Indirect Address Register ......................................... 172
SFR Definition 17.2. LINDATA: LIN Data Register ..................................................... 172
SFR Definition 17.3. LINCF Control Mode Register ................................................... 173
SFR Definition 17.4. LIN0DT1: LIN0 Data Byte 1 ....................................................... 174
SFR Definition 17.5. LIN0DT2: LIN0 Data Byte 2 ....................................................... 175
SFR Definition 17.6. LIN0DT3: LIN0 Data Byte 3 ....................................................... 175
SFR Definition 17.7. LIN0DT4: LIN0 Data Byte 4 ....................................................... 175
SFR Definition 17.8. LIN0DT5: LIN0 Data Byte 5 ....................................................... 176
SFR Definition 17.9. LIN0DT6: LIN0 Data Byte 6 ....................................................... 176
SFR Definition 17.10. LIN0DT7: LIN0 Data Byte 7 ..................................................... 176
SFR Definition 17.11. LIN0DT8: LIN0 Data Byte 8 ..................................................... 176
SFR Definition 17.12. LIN0CTRL: LIN0 Control Register ........................................... 177
SFR Definition 17.13. LIN0ST: LIN0 STATUS Register ............................................. 178
SFR Definition 17.14. LIN0ERR: LIN0 ERROR Register ............................................ 179
SFR Definition 17.15. LIN0SIZE: LIN0 Message Size Register .................................. 180
SFR Definition 17.16. LIN0DIV: LIN0 Divider Register ............................................... 180
SFR Definition 17.17. LIN0MUL: LIN0 Multiplier Register .......................................... 181
SFR Definition 17.18. LIN0ID: LIN0 ID Register ......................................................... 181
SFR Definition 18.1. TCON: Timer Control ................................................................. 186
SFR Definition 18.2. TMOD: Timer Mode ................................................................... 187
SFR Definition 18.3. CKCON: Clock Control .............................................................. 188
SFR Definition 18.4. TL0: Timer 0 Low Byte ............................................................... 189
SFR Definition 18.5. TL1: Timer 1 Low Byte ............................................................... 189
SFR Definition 18.6. TH0: Timer 0 High Byte ............................................................. 189
SFR Definition 18.7. TH1: Timer 1 High Byte ............................................................. 189
SFR Definition 18.8. TMR2CN: Timer 2 Control ......................................................... 193
SFR Definition 18.9. TMR2RLL: Timer 2 Reload Register Low Byte .......................... 194
SFR Definition 18.10. TMR2RLH: Timer 2 Reload Register High Byte ...................... 194
SFR Definition 18.11. TMR2L: Timer 2 Low Byte ....................................................... 194
SFR Definition 18.12. TMR2H Timer 2 High Byte ....................................................... 194
SFR Definition 19.1. PCA0CN: PCA Control .............................................................. 206
11 Rev. 1.4

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