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PDF C8051F551 Data sheet ( Hoja de datos )

Número de pieza C8051F551
Descripción Mixed Signal ISP Flash MCU
Fabricantes Silicon Laboratories 
Logotipo Silicon Laboratories Logotipo



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Analog Peripherals
- 12-Bit ADC
Up to 200 ksps
Up to 32 external single-ended inputs
VREF from on-chip VREF, external pin or VDD
Internal or external start of conversion source
Built-in temperature sensor
- Two Comparators
Programmable hysteresis and response time
Configurable as interrupt or reset source
Low current
On-Chip Debug
- On-chip debug circuitry facilitates full speed, non-
intrusive in-system debug (no emulator required)
- Provides breakpoints, single stepping,
inspect/modify memory and registers
- Superior performance to emulation systems using
ICE-chips, target pods, and sockets
- Low cost, complete development kit
Supply Voltage 1.8 to 5.25 V
- Typical operating current: 19 mA at 50 MHz
- Typical stop mode current: 1 µA
High-Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
- Up to 50 MIPS throughput with 50 MHz clock
- Expanded interrupt handler
C8051F55x/56x/57x
Mixed Signal ISP Flash MCU Family
Memory
- 2304 bytes internal data RAM (256 + 2048 XRAM)
- 32 or 16 kB Flash; In-system programmable in
512-byte Sectors
Digital Peripherals
- 33, 25, or 18 Port I/O; All 5 V tolerant
- CAN 2.0 Controller—no crystal required
- LIN 2.1 Controller (Master and Slave capable); no
crystal required
- Hardware enhanced UART, SMBus™, and
enhanced SPI™ serial ports
- Four general purpose 16-bit counter/timers
- 16-bit programmable counter array (PCA) with six
capture/compare modules and enhanced PWM
functionality
Clock Sources
- Internal 24 MHz with ±0.5% accuracy for CAN and
master LIN operation
- External oscillator: Crystal, RC, C, or clock
(1 or 2 pin modes)
- Can switch between clock sources on-the-fly;
useful in power saving modes
Packages
- 40-pin QFN (C8051F568-9 and ‘F570-5)
- 32-pin QFP/QFN (C8051F560-7)
- 24-pin QFN (C8051F550-7)
Automotive Qualified
- Temperature Range: –40 to +125 °C
- Compliant to AEC-Q100
ANALOG
PERIPHERALS
A 12-bit
M
U
200 ksps
X ADC
TEMP
SENSOR
Voltage VREG
Comparators 0-1 VREF
DIGITAL I/O
UART 0
SMBus
SPI
PCA
Timers 0-3
CAN
LIN
Ports 0-4
Crossbar
External
Memory
Interface
24 MHz PRECISION
INTERNAL OSCILLATOR
2x Clock Multiplier
HIGH-SPEED CONTROLLER CORE
32 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
8051 CPU
(50 MIPS)
DEBUG
CIRCUITRY
2 kB XRAM
POR WDT
Rev. 1.2 9/14
Copyright © 2014 by Silicon Laboratories C8051F55x, C8051F56x, C8051F57x

1 page




C8051F551 pdf
C8051F55x/56x/57x
17.6. Timing .......................................................................................................... 151
17.6.1. Multiplexed Mode .................................................................................. 153
18. Oscillators and Clock Selection ......................................................................... 157
18.1. System Clock Selection................................................................................. 157
18.2. Programmable Internal Oscillator .................................................................. 159
18.2.1. Internal Oscillator Suspend Mode ......................................................... 159
18.3. Clock Multiplier .............................................................................................. 162
18.4. External Oscillator Drive Circuit..................................................................... 164
18.4.1. External Crystal Example...................................................................... 166
18.4.2. External RC Example............................................................................ 167
18.4.3. External Capacitor Example.................................................................. 167
19. Port Input/Output ................................................................................................. 169
19.1. Port I/O Modes of Operation.......................................................................... 170
19.1.1. Port Pins Configured for Analog I/O...................................................... 170
19.1.2. Port Pins Configured For Digital I/O...................................................... 170
19.1.3. Interfacing Port I/O in a Multi-Voltage System ...................................... 171
19.2. Assigning Port I/O Pins to Analog and Digital Functions............................... 171
19.2.1. Assigning Port I/O Pins to Analog Functions ........................................ 171
19.2.2. Assigning Port I/O Pins to Digital Functions.......................................... 171
19.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions ... 172
19.3. Priority Crossbar Decoder ............................................................................. 172
19.4. Port I/O Initialization ...................................................................................... 174
19.5. Port Match ..................................................................................................... 179
19.6. Special Function Registers for Accessing and Configuring Port I/O ............. 183
20. Local Interconnect Network (LIN0)..................................................................... 193
20.1. Software Interface with the LIN Controller..................................................... 194
20.2. LIN Interface Setup and Operation................................................................ 194
20.2.1. Mode Definition ..................................................................................... 194
20.2.2. Baud Rate Options: Manual or Autobaud ............................................. 194
20.2.3. Baud Rate Calculations: Manual Mode................................................. 194
20.2.4. Baud Rate Calculations—Automatic Mode ........................................... 196
20.3. LIN Master Mode Operation .......................................................................... 197
20.4. LIN Slave Mode Operation ............................................................................ 198
20.5. Sleep Mode and Wake-Up ............................................................................ 199
20.6. Error Detection and Handling ........................................................................ 199
20.7. LIN Registers................................................................................................. 200
20.7.1. LIN Direct Access SFR Registers Definitions ....................................... 200
20.7.2. LIN Indirect Access SFR Registers Definitions ..................................... 202
21. Controller Area Network (CAN0) ........................................................................ 210
21.1. Bosch CAN Controller Operation................................................................... 211
21.1.1. CAN Controller Timing .......................................................................... 211
21.1.2. CAN Register Access............................................................................ 212
21.1.3. Example Timing Calculation for 1 Mbit/Sec Communication ................ 212
21.2. CAN Registers............................................................................................... 214
21.2.1. CAN Controller Protocol Registers........................................................ 214
Rev. 1.2
5

5 Page





C8051F551 arduino
C8051F55x/56x/57x
List of Tables
Table 2.1. Product Selection Guide ......................................................................... 21
Table 3.1. Pin Definitions for the C8051F55x/56x/57x ............................................ 22
Table 4.1. QFN-40 Package Dimensions ................................................................ 28
Table 4.2. QFN-40 Landing Diagram Dimensions ................................................... 29
Table 4.3. QFP-32 Package Dimensions ................................................................ 30
Table 4.4. QFP-32 Landing Diagram Dimensions ................................................... 31
Table 4.5. QFN-32 Package Dimensions ................................................................ 32
Table 4.6. QFN-32 Landing Diagram Dimensions ................................................... 33
Table 4.7. QFN-24 Package Dimensions ................................................................ 34
Table 4.8. QFN-24 Landing Diagram Dimensions ................................................... 35
Table 5.1. Absolute Maximum Ratings .................................................................... 36
Table 5.2. Global Electrical Characteristics ............................................................. 37
Table 5.3. Port I/O DC Electrical Characteristics ..................................................... 40
Table 5.4. Reset Electrical Characteristics .............................................................. 41
Table 5.5. Flash Electrical Characteristics .............................................................. 41
Table 5.6. Internal High-Frequency Oscillator Electrical Characteristics ................. 42
Table 5.7. Clock Multiplier Electrical Specifications ................................................ 43
Table 5.8. Voltage Regulator Electrical Characteristics .......................................... 43
Table 5.9. ADC0 Electrical Characteristics .............................................................. 44
Table 5.10. Temperature Sensor Electrical Characteristics .................................... 45
Table 5.11. Voltage Reference Electrical Characteristics ....................................... 45
Table 5.12. Comparator 0 and Comparator 1 Electrical Characteristics ................. 46
Table 10.1. CIP-51 Instruction Set Summary .......................................................... 84
Table 12.1. Special Function Register (SFR) Memory Map for Pages 0x00 and 0x0F
106
Table 12.2. Special Function Register (SFR) Memory Map for Page 0x0C .......... 107
Table 12.3. Special Function Registers ................................................................. 108
Table 13.1. Interrupt Summary .............................................................................. 114
Table 14.1. Flash Security Summary .................................................................... 128
Table 17.1. EMIF Pinout (C8051F568-9 and ‘F570-5) .......................................... 146
Table 17.2. AC Parameters for External Memory Interface ................................... 156
Table 19.1. Port I/O Assignment for Analog Functions ......................................... 171
Table 19.2. Port I/O Assignment for Digital Functions ........................................... 172
Table 19.3. Port I/O Assignment for External Digital Event Capture Functions .... 172
Table 20.1. Baud Rate Calculation Variable Ranges ............................................ 194
Table 20.2. Manual Baud Rate Parameters Examples ......................................... 196
Table 20.3. Autobaud Parameters Examples ........................................................ 197
Table 20.4. LIN Registers* (Indirectly Addressable) .............................................. 202
Table 21.1. Background System Information ........................................................ 212
Table 21.2. Standard CAN Registers and Reset Values ....................................... 215
Table 22.1. SMBus Clock Source Selection .......................................................... 222
Table 22.2. Minimum SDA Setup and Hold Times ................................................ 223
Rev. 1.2
11

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