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PDF CAT523 Data sheet ( Hoja de datos )
| Número de pieza | CAT523 | |
| Descripción | Configured Digitally Programmable Potentiometer (DPP): Programmable Voltage Applications | |
| Fabricantes | Catalyst Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CAT523 (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
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Advance Information
CAT523
Configured Digitally Programmable Potentiometer (DPP): Programmable Voltage Applications
FEATURES
s Two 8-bit DPPS Configured as Programmable
Voltages in DAC-like Applications
s Buffered Wiper Outputs
s Nonvolatile Wiper Storage
s Output voltage range includes both supply rails
s 2 independently addressable output wipers
s 1 LSB Accuracy, High Resolution
s Serial µP interface
s Single supply operation: 2.7V-5.5V
s Setting read-back without effecting outputs
APPLICATIONS
s Automated product calibration.
s Remote control adjustment of equipment
s Offset, gain and zero adjustments in Self-
Calibrating and Adaptive Control systems.
s Tamper-proof calibrations.
s DAC (with memory) substitute
DESCRIPTION
The CAT523 is a dual, 8-bit digitally-programmable
potentiometer configured for programmable voltage and
DAC-like applications. Intended for final calibration of
products such as camcorders, fax machines and cellular
telephones on automated high volume production lines,
it is also well suited for systems capable of self
calibration, and applications where equipment which is
either difficult to access or in a hazardous environment,
requires periodic adjustment.
The 2 independently programmable DPPs have a
common output voltage range which includes both
supply rails. The wipers are buffered by rail to rail OP
AMPS. Wiper settings, stored in non-volatile memory,
are not lost when the device is powered down and are
automatically reinstated when power is returned. Each
wiper can be dithered to test new output values without
effecting the stored settings and stored settings can be
read back without disturbing the DAC’s output.
Control of the CAT523 is accomplished with a simple 3
wire serial interface. A Chip Select pin allows several
CAT523's to share a common serial interface and
communication back to the host controller is via a single
serial data line thanks to the CAT523’s Tri-Stated Data
Output pin. A RDY/BSY output working in concert with
an internal low voltage detector signals proper operation
of non-volatile Erase/Write cycle.
The CAT523 is available in the 0 to 70° C Commercial
and –40° C to + 85° C Industrial operating temperature
ranges and offered in 14-pin plastic DIP and SOIC
mount packages.
FUNCTIONAL DIAGRAM
PIN CONFIGURATION
PROG
7
RDY/BSY
3
PROGRAM
CONTROL
5
DI
CLK
2
4
CS
SERIAL
CONTROL
VDD
1
DATA
REGISTER
AND
NONVOLATILE
MEMORY
VREFH
14
7KΩ
7KΩ
+
+
13
VOUT1
12
VOUT2
DIP Package (P)
VDD
CLK
RDY/BSY
CS
DI
DO
PROG
1 14
2 13
3 12
4 CAT 11
523
5 10
69
78
VREFH
VOUT1
VOUT2
NC
NC
VREFL
GND
SOIC Package (J)
VDD
CLK
RDY/BSY
CS
DI
DO
PROG
1 14
2 13
3 12
4 CAT 11
5 523 10
69
78
VREFH
VOUT1
VOUT2
NC
NC
VREFL
GND
CAT523
8
GND
SERIAL
DATA
OUTPUT
REGISTER
9
VREF L
© 2001 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
6
DO
1
Doc. No. 25076-00 2/98 M-1
1 page  
Advance Information
PIN DESCRIPTION
Pin Name Function
1 VDD Power supply positive.
2 CLK Clock input pin.Clock input pin.
3 RDY/BSY Ready/Busy Output
4 CS Chip Select
5 DI Serial data input pin.
6 DO Serial data output pin.
7 PROG EEPROM Programming Enable
Input
8
GND
Power supply ground.
9
VREFL
Minimum DAC output voltage.
10 NC No Connect.
11 NC No Connect.
12
VOUT2
DAC output channel 2.
13
VOUT1
DAC output channel 1.
14
VREFH
Maximum DAC output voltage.
CAT523
DAC addressing is as follows:
DAC OUTPUT
VOUT1
VOUT2
A0 A1
00
10
DEVICE OPERATION
The CAT523 is a quad 8-bit Digital to Analog Converter
(DAC) whose outputs can be programmed to any one of
256 individual voltage steps. Once programmed, these
output settings are retained in non-volatile EEPROM
memory and will not be lost when power is removed from
the chip. Upon power up the DACs return to the settings
stored in EEPROM memory. Each DAC can be written
to and read from independently without effecting the
output voltage during the read or write cycle. Each
output can also be temporarily adjusted without chang-
ing the stored output setting, which is useful for testing
new output settings before storing them in memory.
DIGITAL INTERFACE
The CAT523 employs a standard 3 wire serial control
interface consisting of Clock (CLK), Chip Select (CS)
and Data In (DI) inputs. For all operations, address and
data are shifted in LSB first. In addition, all digital data
must be preceded by a logic “1” as a start bit. The DAC
address and data are clocked into the DI pin on the
clock’s rising edge. When sending multiple blocks of
information a minimum of two clock cycles is required
between the last block sent and the next start bit.
Multiple devices may share a common input data line by
selectively activating the CS control of the desired IC.
Data Outputs (DO) can also share a common line
because the DO pin is Tri-Stated and returns to a high
impedance when not in use.
CHIP SELECT
Chip Select (CS) enables and disables the CAT523’s
read and write operations. When CS is high data may be
read to or from the chip, and the Data Output (DO) pin is
active. Data loaded into the DAC control registers will
remain in effect until CS goes low. Bringing CS to a logic
low returns all DAC outputs to the settings stored in
EEPROM memory and switches DO to its high imped-
ance Tri-State mode.
Because CS functions like a reset the CS pin has been
equipped with a 30 ns to 90 ns filter circuit to prevent
noise spikes from causing unwanted resets and the loss
of volatile data.
CLOCK
The CAT523’s clock controls both data flow in and out of
the IC and EEPROM memory cell programming. Serial
data is shifted into the DI pin and out of the DO pin on the
clock’s rising edge. While it is not necessary for the clock
to be running between data transfers, the clock must be
operating in order to write to EEPROM memory, even
though the data being saved may already be resident in
the DAC control register.
No clock is necessary upon system power-up. The
CAT523’s internal power-on reset circuitry loads data
from EEPROM to the DACs without using the external
clock.
As data transfers are edge triggered clean clock transi-
tions are necessary to avoid falsely clocking data into the
control registers. Standard CMOS and TTL logic fami-
lies work well in this regard and it is recommended that
any mechanical switches used for breadboarding or
device evaluation purposes be debounced by a flip-flop
or other suitable debouncing circuit.
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet CAT523.PDF ] | |
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