DataSheet.es    


PDF R5F21344CDFP Data sheet ( Hoja de datos )

Número de pieza R5F21344CDFP
Descripción MCU
Fabricantes Renesas 
Logotipo Renesas Logotipo



Hay una vista previa y un enlace de descarga de R5F21344CDFP (archivo pdf) en la parte inferior de esta página.


Total 30 Páginas

No Preview Available ! R5F21344CDFP Hoja de datos, Descripción, Manual

Datasheet
R8C/34C Group
RENESAS MCU
R01DS0007EJ0100
Rev 1.00
Aug. 24, 2010
1. Overview
1.1 Features
The R8C/34C Group of single-chip MCUs incorporates the R8C CPU core, employing sophisticated instructions
for a high level of efficiency. With 1 Mbyte of address space, and it is capable of executing instructions at high
speed. In addition, the CPU core boasts a multiplier for high-speed operation processing.
Power consumption is low, and the supported operating modes allow additional power control. These MCUs are
designed to maximize EMI/EMS performance.
Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of
system components.
The R8C/34C Group has data flash (1 KB × 4 blocks) with the background operation (BGO) function.
1.1.1 Applications
Electronic household appliances, office equipment, audio equipment, consumer equipment, etc.
R01DS0007EJ0100 Rev 1.00
Aug. 24, 2010
Page 1 of 54

1 page




R5F21344CDFP pdf
R8C/34C Group
1.3 Block Diagram
Figure 1.2 shows a Block Diagram.
1. Overview
8
8
8
6 51
8
I/O ports
Port P0
Port P1
Port P2
Port P3
Port P4
Port P6
Peripheral functions
Timers
Timer RA (8 bits × 1)
Timer RB (8 bits × 1)
Timer RC (16 bits × 1)
Timer RD (16 bits × 2)
Timer RE (8 bits × 1)
Watchdog timer
(14 bits)
A/D converter
(10 bits × 12 channels)
D/A converter
(8 bits × 2)
UART or
clock synchronous serial I/O
(8 bits × 3)
I2C bus or SSU
(8 bits × 1)
LIN module
Comparator B
System clock generation
circuit
XIN-XOUT
High-speed on-chip oscillator
Low-speed on-chip oscillator
XCIN-XCOUT
Low-speed on-chip oscillator
for watchdog timer
Voltage detection circuit
DTC
Figure 1.2 Block Diagram
R8C CPU core
R0H R0L
R1H R1L
R2
R3
A0
A1
FB
SB
USP
ISP
INTB
PC
FLG
Memory
ROM (1)
RAM (2)
Multiplier
Notes:
1. ROM size varies with MCU type.
2. RAM size varies with MCU type.
R01DS0007EJ0100 Rev 1.00
Aug. 24, 2010
Page 5 of 54

5 Page





R5F21344CDFP arduino
R8C/34C Group
2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a
register bank. There are two sets of register bank.
b31
R2
R3
b15 b8b7
b0
R0H (high-order of R0) R0L (low-order of R0)
R1H (high-order of R1) R1L (low-order of R1)
R2
R3
A0
A1
FB
Data registers (1)
Address registers (1)
Frame base register (1)
b19 b15
INTBH
INTBL
The 4 high order bits of INTB are INTBH and
the 16 low order bits of INTB are INTBL.
b19
PC
b0
b0
Interrupt table register
Program counter
b15 b0
USP
ISP
SB
b15 b0
FLG
b15
IPL
b8 b7
b0
U I OB S ZDC
Note:
1. These registers comprise a register bank. There are two register banks.
Figure 2.1 CPU Registers
User stack pointer
Interrupt stack pointer
Static base register
Flag register
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
Reserved bit
R01DS0007EJ0100 Rev 1.00
Aug. 24, 2010
Page 11 of 54

11 Page







PáginasTotal 30 Páginas
PDF Descargar[ Datasheet R5F21344CDFP.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
R5F21344CDFPMCURenesas
Renesas

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar