DataSheet.es    


PDF R5F21238KFP Data sheet ( Hoja de datos )

Número de pieza R5F21238KFP
Descripción MCU
Fabricantes Renesas 
Logotipo Renesas Logotipo



Hay una vista previa y un enlace de descarga de R5F21238KFP (archivo pdf) en la parte inferior de esta página.


Total 30 Páginas

No Preview Available ! R5F21238KFP Hoja de datos, Descripción, Manual

R8C/22 Group, R8C/23 Group
RENESAS MCU
REJ03B0097-0200
Rev.2.00
Aug 20, 2008
1. Overview
This MCU is built using the high-performance silicon gate CMOS process using the R8C CPU core and is packaged
in a 48-pin plastic molded LQFP. This MCU operates using sophisticated instructions featuring a high level of
instruction efficiency. With 1 Mbyte of address space, it is capable of executing instructions at high speed. This MCU
is equipped with one CAN module and suited to in-vehicle or FA networking.
Furthermore, the data flash (1 KB x 2 blocks) is embedded in the R8C/23 Group.
The difference between R8C/22 and R8C/23 Groups is only the existence of the data flash. Their peripheral functions
are the same.
1.1 Applications
Automotive, etc.
Rev.2.00 Aug 20, 2008 Page 1 of 48
REJ03B0097-0200

1 page




R5F21238KFP pdf
R8C/22 Group, R8C/23 Group
1. Overview
1.4 Product Information
Table 1.3 lists Product Information for R8C/22 Group and Table 1.4 lists Product Information for R8C/23 Group.
Table 1.3 Product Information for R8C/22 Group
Current of Aug. 2008
Type No.
R5F21226DFP
R5F21227DFP
R5F21228DFP
R5F21226JFP
R5F21227JFP
R5F21228JFP
R5F2122AJFP
R5F2122CJFP
R5F21226KFP
R5F21227KFP
R5F21228KFP
R5F2122AKFP
R5F2122CKFP
ROM Capacity
32 Kbytes
48 Kbytes
64 Kbytes
32 Kbytes
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes(1)
32 Kbytes
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes(1)
RAM Capacity Package Type
2 Kbytes
PLQP0048KB-A
2.5 Kbytes PLQP0048KB-A
3 Kbytes
PLQP0048KB-A
2 Kbytes
PLQP0048KB-A
2.5 Kbytes PLQP0048KB-A
3 Kbytes
PLQP0048KB-A
5 Kbytes
PLQP0048KB-A
6 Kbytes
PLQP0048KB-A
2 Kbytes
PLQP0048KB-A
2.5 Kbytes PLQP0048KB-A
3 Kbytes
PLQP0048KB-A
5 Kbytes
PLQP0048KB-A
6 Kbytes
PLQP0048KB-A
Remarks
D version Flash memory
version
J version
K version
NOTE:
1. Do not use addresses 20000h to 23FFFh because these areas are used for the emulator debugger.
Refer to 24. Notes on Emulator Debugger of Hardware Manual.
Part number R 5 F 21 22 6 J XXX FP
Package type:
FP: PLQP0048KB-A
(0.5 mm pin-pitch, 7 mm square body)
ROM number
Classification
D: Operating ambient temperature -40°C to 85°C (D version)
J: Operating ambient temperature -40°C to 85°C (J version)
K: Operating ambient temperature -40°C to 125°C (K version)
ROM capacity
6: 32 KB
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/22 Group
R8C/2x Series
Memory type
F: Flash memory version
Renesas MCU
Renesas semiconductors
Figure 1.2 Type Number, Memory Size, and Package of R8C/22 Group
Rev.2.00 Aug 20, 2008 Page 5 of 48
REJ03B0097-0200

5 Page





R5F21238KFP arduino
R8C/22 Group, R8C/23 Group
2. Central Processing Unit (CPU)
2.1 Data Registers (R0, R1, R2 and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3.
R0 can be split into high-order bit (R0H) and low-order bit (R0L) to be used separately as 8-bit data registers. The
same applies to R1H and R1L as R0H and R0L. R2 can be combined with R0 to be used as a 32-bit data register
(R2R0). The same applies R3R1 as R2R0.
2.2 Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. They also
are used for transfer, arithmetic and logic operations. The same applies to A1 as A0.
A1 can be combined with A0 to be used a 32-bit address register (A1A0).
2.3 Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB, a 20-bit register, indicates the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC, 20 bits wide, indicates the address of an instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointer (SP), USP and ISP, are 16 bits wide each.
The U flag of FLG is used to switch between USP and ISP.
2.7 Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8 Flag Register (FLG)
FLG is a 11-bit register indicating the CPU status.
2.8.1 Carry Flag (C)
The C flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic and logic unit.
2.8.2 Debug Flag (D)
The D flag is for debug only. Set to 0.
2.8.3 Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation resulted in 0; otherwise, 0.
2.8.4 Sign Flag (S)
The S flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, 0.
2.8.5 Register Bank Select Flag (B)
The register bank 0 is selected when the B flag is 0. The register bank 1 is selected when this flag is set to 1.
2.8.6 Overflow Flag (O)
The O flag is set to 1 when the operation resulted in an overflow; otherwise, 0.
Rev.2.00 Aug 20, 2008 Page 11 of 48
REJ03B0097-0200

11 Page







PáginasTotal 30 Páginas
PDF Descargar[ Datasheet R5F21238KFP.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
R5F21238KFPMCURenesas
Renesas

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar