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PDF MAP3702 Data sheet ( Hoja de datos )

Número de pieza MAP3702
Descripción 600kHz 1-CH White LED Driver
Fabricantes MagnaChip 
Logotipo MagnaChip Logotipo



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No Preview Available ! MAP3702 Hoja de datos, Descripción, Manual

Confidential
Datasheet Version 1.1
Preliminary Datasheet - MAP3702
600kHz 1-CH White LED Driver for Mobile Backlight
General Description
MAP3702 is an 1-channel LED driver optimized for
LED backlight application targeting mobile LCD
module.
MAP3702 uses 40V absolute Max. rating boost
MOSFET internally and input voltage is ranged from
2.7V ~ 5.5V. The boost converter runs at 600kHz fixed
switching frequency. The default LED current is set by
external resistor and the feedback voltage is regulated
up to 200mV.
Two dimming controls are available; 32 dimming
steps using the SWIRE interface and filtered-PWM
control.
MAP3702 has various protections like over-current,
output over-voltage protection for open-LED faults,
thermal shutdown and UVLO.
MAP3702 is available 2mm X 2mm 6 leads DFN
package with Halogen-free (fully RoHS compliant).
Features
2.7V to 5.5V input voltage range
37V open LED protection
Up to 90% Efficiency
600kHz switching frequency
Internal boost MOSFET
200mV reference voltage with 2% accuracy
Flexible 32-steps single-wire digital and
filtered-PWM brightness control
Bulilt-in soft-start
UVLO
Thermal shutdown
2mmX 2mm 6-pin DFN package
Applications
Mobile hansets
Tablets
Ditital still cameras(DSC)
Ordering Information
Part Number
MAP3702DFRH
Top
Marking
MAP3702
Ambient
Temperature Range
-40to +85
Typical Application
Package
2.0mmX2.0mm DFN
RoHS Status
Halogen Free
Jun 28th 2013

1 page




MAP3702 pdf
Confidential
Typical Operating Characteristics
Unless otherwise noted, VIN = 3.6V, Cin=4.7uF, Cout=1uF, RISET=10Ω and TA = 25°C.
VFB vs. STEP
Datasheet Version 1.1
VFB vs. PWM duty.
Efficiency vs. LED Current
Efficiency vs. VIN(10 LEDs)
fSW vs. VIN
fSW vs. Temp
Jun 28th 2013

5 Page





MAP3702 arduino
Confidential
Datasheet Version 1.1
SWIRE INTERFACE PROTOCOL
The interface is based on a master-slave structure, where the master is typically a microcontroller or application
processor. The protocol consists of a device specific address byte and a data byte. The device specific address
byte is fixed to 72 hex. The data byte consists of five bits for information, two address bits, and the RFA bit. The
RFA bit set to high indicates the Request for Acknowledge condition. The Acknowledge condition is only applied if
the protocol was received correctly. The SWRIE interface can automatically detect bit rates between 1.7kBit/sec
and up to 160kBit/sec.
Byte
Device
Address
(72
HEX)
bit
no.
7
6
5
4
3
2
1
0
Name
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
Transmission
Direction
IN
Description
0(MSB)
1
1
1
0
0
1
0(LSB)
Byte
Data
bit
no.
Name
Transmission
Direction
Description
7 RFA
RFA(Note 1)
6 A1
0(Address)
5 A0
0(Address)
4 D4
3 D3
IN
Data bit 4
Data bit 3
2 D2
Data bit 2
1 D1
Data bit 1
0 D0
Data bit 0
ACK
OUT
(Note 2)
Note 1. Request For Acknowledge, If High, acknowledge is applied by device
Note 2. Acknowledge condition active 0, this condition will only be applied in case RFA bit is set. Open drain output.
Line needs to be pulled high by the host with a pull-up resistor. This feature can only be used if the master
has an open drain output stage. In case of a push-pull output stage acknowledge condition may not be
requested.
The bit detection is based on a Logic Detection scheme, where the criterion is the relation between logic low time
and logic high time.
Low Bit: tL_LB(Low time Low bit) > 2*tH_LB(High time Low bit)
High Bit: tH_HB(High time High bit) > 2*tL_HB(Low time High bit)
The bit detection starts with a falling edge on the CTRL pin and ends with the next falling edge.
All bits are transmitted MSB first and LSB last. Following figures show the protocol without acknowledge request
(bit RFA = 0) and with acknowledge (bit RFA = 1) request. Prior to both bytes, device address byte and data byte, a
start condition must be applied. For this, the CTRL pin must be pulled high for at least tSTART(2µs) before the bit
transmission starts with the falling edge. If the CTRL pin is already at a high level, no start condition is needed prior
to the device address byte. The transmission of each byte is closed with an End Of Stream(EOS) condition for at
least tEOS(2µs).
Jun 28th 2013

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