|
|
PDF MAP7102 Data sheet ( Hoja de datos )
| Número de pieza | MAP7102 | |
| Descripción | Dual Output LCD Bias IC | |
| Fabricantes | MagnaChip | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MAP7102 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
|
No Preview Available !
Confidential
Datasheet Version 1.1
MAP7102
Dual Output LCD Bias IC
General Description
The MAP7102 is designed to support positive
/ negative driven TFT-LCD panels. The two
output rails are usually connected to the
Source Driver IC. The device uses a single
inductor scheme in order to provide the user
the smallest solution size possible as well as
high efficiency. With its input voltage range of
2.8V to 5.5V, it is optimized for products
powered by single-cell batteries and output
currents up to 50mA.
The device is delivered in a WLCSP package
of 15 balls.
Application :
• TFT LCD Smartphones
• TFT LCD Tablets
• General Dual Power Supply Applications
Features
• SIMO(Single-Inductor Multiple output) regulator
Technology
• 86% Efficiency for 20mA Load current Between
+5.0V and -5.0V.
• 2.8V to 5.5V Input Voltage Range
• Under-Voltage Lockout Rising/Falling
• Programmable Output Voltages
• Positive Output Voltage Range : 4.0V to 5.7V
( 0.1V Step )
• Negative Output Voltage Range : -4.0V to -5.7V
( 0.1V Step )
• 1%(Typ.) Output Voltage Accuracy
• Maximum Output Current : 50mA
• Programmable Active Discharge
• Excellent Line Regulation
• Advanced Power-Save Mode for Light-load
Efficient
• Integrated Compensation and Feedback circuits
• Fully integrated FETs for Synchronous rectification
• Short Circuit Protection
• Thermal Shutdown Protection
• 15-Ball WLCSP Package
Ordering Information
Part Number
MAP7102WCRH
Top
Marking
7102
LLL
YWNMM
Junction
Temperature Range
-40℃ to +85℃
Package
15 bump 0.4mm pitch CSP
RoHS Status
Halogen Free
Mar. 2015. Revision 1.1
1 MagnaChip Semiconductor Ltd.
1 page  
Confidential
Datasheet Version 1.1
ELECTRICAL CHARACTERISTICS
VIN = 3.8 V, ENN = ENP = VIN, VPOS = 5.0 V, VNEG = –5.0 V, TA = –40°C to 85°C; typical values are at TA = 25°C
(unless otherwise noted).
Symbol
Parameter
General Section
VIN Input Voltage Range
VUVLO
Under Voltage Lock Out
IQ(ON)
Quiescent Current
IQ(OFF) Shutdown Current
VIH Enable High Threshold
VIL Enable Low Threshold
REN Enable Pull down resistance
TSD Thermal Shutdown Temperature
TSD_HYS
Thermal Shutdown Hysteresis
Boost Converter_ VREG
ILIMVREG
VREG Current Limit
FSW Boost Switching Frequency
RONLXPG
Internal MOSFET Switch ON-
Resistance from LXP to GND
RONLXPO
Internal MOSFET Switch ON-
Resistance from LXP to VBST
ILXPLX
LX Leakage Current
tss Soft Start time
Negative Charge Pump Output _ VNEG
VNEG
Negative Output Voltage Range
VNEG Output voltage Accuracy
FSWN
Charge Pump Switching
Frequency
Line Regulation
Load Regulation
ICPLX
CP Leakage Current
RDISCH
Discharge Resistance
tSSVNEG
VNEG Soft Start time
LDO Output _ VPOS
VPOS
Positive Output Voltage Range
VPOS Output voltage Accuracy
VDRP1
ILDOLX
RDISCH
tSSVPOS
Dropout Voltage LDO
Line Regulation
Load Regulation
VPOS Leakage Current
Discharge Resistance
VPOS Soft Start time
Test Conditions
Rising Threshold voltage
Falling Threshold Voltage
Enable=High, Switching Mode
Enable=Low
EN_P/N(Note1)
(Note1)
(Note1)
(Note1)
IOUT= 100mA (Note1)
IOUT= 100mA (Note1)
VLXP=5.0V, EN=0V
(Note1)
2.8V<VIN<5.5V
TA = –40°C to 85°C
∆VIN=1V, INEG=30mA(Note1)
(Note1)
VCP=6.0V, EN=0V
(Note1)
(Note1)
2.8V<VIN<5.5V
TA = –40°C to 85°C
IPOS=100mA
∆VIN=1V, IPOS=30mA(Note1)
(Note1)
VPOS=0V, EN=0V
(Note1)
(Note1)
Min.
2.8
1.2
0.9
1.44
-4.0
-1.5
0.8
4.0
-1.5
Typ.
2.6
2.1
1.3
1
200
140
10
1.2
1.8
175
240
0.7
1.0
0.04
0.19
20
0.7
0.04
0.31
70
0.7
Max.
5.5
2.8
2.3
3
0.4
Unit
V
V
V
mA
uA
V
V
kΩ
℃
℃
1.5
2.25
A
MHz
mΩ
mΩ
10 uA
2 ms
-5.7 V
1.5 %
1.2 MHz
%/V
%/50mA
10 uA
Ω
2 ms
5.7 V
1.5 %
100 mV
%/V
%/50mA
1 uA
Ω
2 ms
Mar. 2015. Revision 1.1
5 MagnaChip Semiconductor Ltd.
5 Page 
Confidential
Datasheet Version 1.1
VIN
ENP
ENN
VREG
VREG power good
VPOS
UVLO
Pull to GND
(70ohm typ)
VIN
ENP
ENN
VREG
VREG power good
VPOS
UVLO
Pull to GND
(70ohm typ)
VNEG
Pull to GND(20ohm typ)
VNEG
Pull to GND
(20ohm typ)
Figure 20: Example of power off sequence activated
by ENP and ENN when VIN is above UVLO
Figure 21: Example of power off sequence activated
by VIN falling below UVLO
REGISTER MAP
Slave Address : 3Eh [ Bit : 0111110x ]
Table 1. I2C Registers
Register R/W Function
00h R/W VPOS
01h R/W VNEG
03h R/W
DIS
BIT 7 BIT 6 BIT 5 BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
VPOS[4] VPOS[3] VPOS[2] VPOS[1] VPOS[0]
Not Used
VNEG[4] VNEG[3] VNEG[2] VNEG[1] VNEG[0]
Not Used
DISP
DISN
Table 2. VPOS/VNEG Voltage Setting
CODE
NO. HEX VPOS VNEG
BIT4
BIT3
BIT2
BIT1
BIT0
10
20
30
40
50
60
70
80
90
10 0
11 0
0
0
0
0
0
0
0
0
1
1
1
0 0 0 00h 4.0V -4.0V
0 0 1 01h 4.1V -4.1V
0 1 0 02h 4.2V -4.2V
0 1 1 03h 4.3V -4.3V
1 0 0 04h 4.4V -4.4V
1 0 1 05h 4.5V -4.5V
1 1 0 06h 4.6V -4.6V
1 1 1 07h 4.7V -4.7V
0 0 0 08h 4.8V -4.8V
0 0 1 09h 4.9V -4.9V
0 1 0 0Ah 5.0V -5.0V
Mar. 2015. Revision 1.1
11 MagnaChip Semiconductor Ltd.
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet MAP7102.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MAP7102 | Dual Output LCD Bias IC | MagnaChip |
| MAP7103 | High Voltage Boost Converter | MagnaChip |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |