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PDF MAP3512 Data sheet ( Hoja de datos )
| Número de pieza | MAP3512 | |
| Descripción | 2-CH Average Current Control Buck Controller | |
| Fabricantes | MagnaChip | |
| Logotipo |  |
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Confidential
Datasheet Version 1.1
Datasheet - MAP3512
2-CH Average Current Control Buck Controller for LED Backlight
General Description
MAP3512 is a 2 channel average-mode current
control buck controller for LED backlight application. It
does not require an additional dimming MOSFET and
utilizes constant off-time control and average current
control feedback without external loop compensation
or high-side current sensing.
MAP3512 features ±1% CS voltage accuracy and
has dedicated analog dimming input up to 3V. It can
be powered from 8.5V ~ 18V supply.
MAP3512 provides MOSFET DS short detection(FLT
output), SCP, ODP and UVLO.
MAP3512 is available 16 leads SOIC with Halogen-
free (fully RoHS compliant).
Features
8.5V to 18V Input Voltage Range
Average-Mode Current Control
Programmable Constant Off-time
Up to 3V Analog Dimming Input
1% CS Voltage Accuracy
Direct PWM Dimming Input
Fault Output(MOSFET Drain-Source Short)
Short Circuit Protection
Over-Duty Protection
UVLO
16 Leads SOIC Package with Halogen-free
Applications
High Brightness white LED backlighting for LCD
TVs
General LED lighting applications
Ordering Information
Part Number
Top
Marking
Ambient
Temperature Range
MAP3512SIRH
MAP3512
-40℃ to +85℃
1
Typical Application
Package
16Leads SOIC
RoHS Status
Halogen Free
VCC
SEL
MODE
PWM1
PWM2
REF
MAP3512
TOFF
GATE1 GATE2
CS1 CS2
PGND1 PGND2
VCC
SEL
MODE
PWM1
PWM2
FLT
ADIM
REF
GND
REF
FLT
Jul 03rd 2015
1 page  
Confidential
Electrical Characteristics
Unless noted, VVCC = 12V, CVCC = 1.0F, and typical values are tested at TA = 25C.
Parameter
Test Condition
Supply
VVCC Input Voltage Range
IQ Quiescent Current
VUVLO
Under Voltage Lockout
Threshold Voltage on VCC pin
Reference
VPWM = 5V, VCS = 0V
Release threshold(rising VVCC)
Lockout hysteresis(falling VVCC)
VREF
Voltage on REF pin
OFF Timer
tOFF GATE1/2 Off-time
tON_MIN Min. On-Time
tON_MAX Max. On-Time
tOFF_MIN Min. Off-Time
DMAX
Max. Duty Cycle
GATE Driver
IREF = 1mA
RTOFF=52kΩ
RTOFF=104kΩ
VADIM = 3V
VADIM = 3V, tOFF=1.2us
ISOURCE GATE1/2 Source Current
ISINK GATE1/2 Sink Current
tRISE GATE1/2 Output Rising Time
tFALL GATE1/2 Output Falling Time
Current Sense & Dimming
VGATE1/2 = 0V,
VGATE1/2 = VVCC=12V
CGATE1/2=1nF, VVCC = 12V
CGATE1/2=1nF, VVCC = 12V
VADIM
AV
ADIM Input Voltage Range
VADIM to CS1/2 Voltage Ratio
VCS1/2 CS1/2 Voltage
5 tLEB Leading Edge Blanking Time
Logic Interface
VADIM = 0.5V
VADIM = 3.0V
VPWM1/2
RPWM1/2
Logic Input Level on
PWM1/2 pins
Pull-down Resistor on PWM1/2 pins
VMODE Logic Input Level on MODE pin
RMODE Pull-down Resistor on MODE pin
VSEL Logic Input Level on SEL pin
RSEL
Pull-down Resistor on SEL pin
Protection
VPWM1/2_L : Logic Low
VPWM1/2_H : Logic High
VPWM1/2 = 4V
VMODE_L : Logic Low
VMODE_H : Logic High
VMODE = 4V
VSEL_L : Logic Low
VSEL_H : Logic High
VSEL = 4V
AVSCP VADIM to SCP Voltage Ratio
VSCP
SCP Detection Threshold Voltage
on CS1/2 pins
tDELAY
tRESTART
VSCPDS
VFLT
DOD1
DOD2
tOD
SCP Delay Time
Restart Time
MOSFET DS Short Detection
Threshold Voltage on CS1/2 pins
FLT pin High Voltage
Protection Duty for OD1
Protection Duty for OD2
Auto-Restart time for OD1/2
0.5 <= VADIM <= 2.5V
VADIM = 0.5V
VADIM = 1.0V
VADIM = 2.5V
VADIM = 0.5V (Note 1, 2)
VADIM = 2.5V (Note 1, 2)
VMODE = GND or Floating
Note 1: These parameters, although guaranteed by design, are not tested in mass production.
Note 2: At start-up(VVCC >= VUVLO release threshold) or VPWMx = Logic ‘High’ at running
Datasheet Version 1.1
Min Typ Max Unit
8.5 18 V
3.4 mA
7.5 8.0 8.5
0.5 1.0 1.5
V
4.95
5.00
5.05
V
4.5 5.0 5.5
9 10 11
300
37
1.2 1.5
97
us
ns
us
us
%
400 mA
800 mA
50 85 ns
25 45 ns
0.5
0.2512
1.5073
0.5075
300
3.0
0.2563
1.5377
V
V/V
V
ns
0.8
V
2.0
50 100 150 kΩ
0.8
V
2.0
50 100 150 kΩ
0.8 V
2.0
50 100 150 kΩ
0.8075
1.6150
4.0375
4.5
55
35
1.7
0.8500
1.7000
4.2500
300
1
0.25
1.25
57
37
200
0.8925
1.7850
4.4625
5
59
39
V/V
V
ns
ms
V
V
%
%
ms
Jul 03rd 2015
5 Page 
Confidential
Datasheet Version 1.1
SCP
If the CS voltage rises VSCP during normal operation, the MAP3512 turns-off the GATE output after tDELAY(typ.
300ns) time. The auto-restart time is typ. 1ms(tRESTART). This protects for hard instantaneous short such as catch
diode, inductor or LED bar short.
tDELAY
tDELAY
GATE
VSCP
CS
tRESTART
MOSFET D-S Short Detection & FLT Output
In case the following drain-source short events of external MOSFET occur, the FLT pin goes to logic HIGH state
immediately. This shuts off the whole system power supply. The protection status is latched and can be cleared by
applying a complete power-on-reset(POR).
CASE(1) : At start-up - Regardless of PWM logic state, if VCS is equal or over than 0.5*VADIM and last over 4us.
FLT pin voltage goes HIGH level before the first GATE output if PWM is logic HIGH state.
CASE(2) : At dimming(PWM=logic HIGH) - At first, SCP will be occured. Even though the GATE is off-state by SCP,
if the CS voltage is equal or over than 1.7*VADIM and last over 30us.
CASE(3) : At other condition(PWM=logic LOW) - If the CS voltage is equal or over than 3.6V and lasts over 4us.
VCC
11 UVLO_H
UVLO_L
PWM
GATE
VCS
0.5 X VADIM
4us
1.7 X VADIM
30us
FLT CASE(1)
CASE(2)
The FLT pin is at logic low state when no error is detected.
4us
3.6V
CASE(3)
Jul 03rd 2015
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet MAP3512.PDF ] | |
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