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PDF CAT28LV256 Data sheet ( Hoja de datos )
| Número de pieza | CAT28LV256 | |
| Descripción | 256K-Bit CMOS PARALLEL E2PROM | |
| Fabricantes | Catalyst Semiconductor | |
| Logotipo |  |
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CAT28LV256
256K-Bit CMOS PARALLEL E2PROM
FEATURES
s 3.0V to 3.6V Supply
s Read Access Times: 200/250/300 ns
s Low Power CMOS Dissipation:
– Active: 15 mA Max.
– Standby: 150 µA Max.
s Simple Write Operation:
– On-Chip Address and Data Latches
– Self-Timed Write Cycle with Auto-Clear
s Fast Write Cycle Time:
– 10ms Max.
s Commercial, Industrial and Automotive
Temperature Ranges
s CMOS and TTL Compatible I/O
s Automatic Page Write Operation:
– 1 to 64 Bytes in 10ms
– Page Load Timer
s End of Write Detection:
– Toggle Bit
– DATA Polling
s Hardware and Software Write Protection
s 100,000 Program/Erase Cycles
s 100 Year Data Retention
DESCRIPTION
The CAT28LV256 is a fast, low power, low voltage
CMOS Parallel E2PROM organized as 32K x 8-bits. It
requires a simple interface for in-system programming.
On-chip address and data latches, self-timed write cycle
with auto-clear and VCC power up/down write protection
eliminate additional timing and protection hardware.
DATA Polling and Toggle status bits signal the start and
end of the self-timed write cycle. Additionally, the
CAT28LV256 features hardware and software write
protection.
BLOCK DIAGRAM
The CAT28LV256 is manufactured using Catalyst’s
advanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC–
approved 28-pin DIP, 28-pin TSOP or 32-pin PLCC
packages.
A6–A14
VCC
CE
OE
WE
A0–A5
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
CONTROL
LOGIC
TIMER
ADDR. BUFFER
& LATCHES
ROW
DECODER
HIGH VOLTAGE
GENERATOR
DATA POLLING
AND
TOGGLE BIT
COLUMN
DECODER
32,768 x 8
E2PROM
ARRAY
64 BYTE PAGE
REGISTER
I/O BUFFERS
I/O0–I/O7
28LV256 F01
© 2001 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25040-00 4/01 P-1
1 page  
Figure 1. A.C. Testing Input/Output Waveform(2)
VCC - 0.3V
0.0 V
INPUT PULSE LEVELS
2.0 V
0.6 V
REFERENCE POINTS
Figure 2. A.C. Testing Load Circuit (example)
Vcc
CAT28LV256
28LV256 F04
DEVICE
UNDER
TEST
1.8K
OUTPUT
1.3K
CL = 100 pF
CL INCLUDES JIG CAPACITANCE
28LV256 F05
A.C. CHARACTERISTICS, Write Cycle
VCC = 3.0V to 3.6V, unless otherwise specified
Symbol
tWC
tAS
tAH
tCS
tCH
tCW(3)
tOES
tOEH
tWP(3)
tDS
tDH
tINIT(1)
tBLC(1)(4)
Parameter
Write Cycle Time
Address Setup Time
Address Hold Time
CE Setup Time
CE Hold Time
CE Pulse Time
OE Setup Time
OE Hold Time
WE Pulse Width
Data Setup Time
Data Hold Time
Write Inhibit Period After Power-up
Byte Load Cycle Time
28LV256-20 28LV256-25 28LV256-30
Min. Max. Min. Max. Min. Max. Units
10 10 10 ms
0 0 0 ns
100 100 100 ns
0 0 0 ns
0 0 0 ns
150 150 150 ns
0 0 0 ns
0 0 0 ns
150 150 150 ns
50 50 50 ns
0 0 0 ns
5 10 5 10 5 10 ms
0.15 100 0.15 100 0.15 100 µs
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Input rise and fall times (10% and 90%) < 10 ns.
(3) A write pulse of less than 20ns duration will not initiate a write cycle.
(4) A timer of duration tBLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin;
however a transition from HIGH to LOW within tBLC max. stops the timer.
5 Doc. No. 25040-00 4/01 P-1
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet CAT28LV256.PDF ] | |
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