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PDF CAT28C64B Data sheet ( Hoja de datos )
| Número de pieza | CAT28C64B | |
| Descripción | 64K-Bit CMOS PARALLEL E2PROM | |
| Fabricantes | Catalyst Semiconductor | |
| Logotipo |  |
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CAT28C64B
64K-Bit CMOS PARALLEL E2PROM
FEATURES
s Fast Read Access Times:
– 120/150ns
s Low Power CMOS Dissipation:
– Active: 25 mA Max.
– Standby: 100 µA Max.
s Simple Write Operation:
– On-Chip Address and Data Latches
– Self-Timed Write Cycle with Auto-Clear
s Fast Write Cycle Time:
– 5ms Max.
s CMOS and TTL Compatible I/O
s Hardware and Software Write Protection
s Commercial, Industrial and Automotive
Temperature Ranges
s Automatic Page Write Operation:
– 1 to 32 Bytes in 5ms
– Page Load Timer
s End of Write Detection:
– Toggle Bit
– DATA Polling
s 100,000 Program/Erase Cycles
s 100 Year Data Retention
DESCRIPTION
The CAT28C64B is a fast, low power, 5V-only CMOS
Parallel E2PROM organized as 8K x 8-bits. It requires a
simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with
auto-clear and VCC power up/down write protection
eliminate additional timing and protection hardware.
DATA Polling and Toggle status bits signal the start and
end of the self-timed write cycle. Additionally, the
CAT28C64B features hardware and software write pro-
tection.
The CAT28C64B is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed to
endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC-
approved 28-pin DIP, 28-pin TSOP, 28-pin SOIC, or, 32-
pin PLCC package .
BLOCK DIAGRAM
A5–A12
ADDR. BUFFER
& LATCHES
ROW
DECODER
8,192 x 8
E2PROM
ARRAY
VCC
INADVERTENT
WRITE
PROTECTION
HIGH VOLTAGE
GENERATOR
32 BYTE PAGE
REGISTER
CE
OE
WE
A0–A4
CONTROL
LOGIC
TIMER
ADDR. BUFFER
& LATCHES
DATA POLLING
AND
TOGGLE BIT
COLUMN
DECODER
I/O BUFFERS
I/O0–I/O7
5094 FHD F02
© 1999 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25006-0A 2/98 P-1
1 page  
CAT28C64B
A.C. CHARACTERISTICS, Read Cycle
VCC = 5V ±10%, unless otherwise specified.
Symbol
tRC
tCE
tAA
tOE
tLZ(1)
tOLZ(1)
tHZ(1)(2)
tOHZ(1)(2)
tOH(1)
Parameter
Read Cycle Time
CE Access Time
Address Access Time
OE Access Time
CE Low to Active Output
OE Low to Active Output
CE High to High-Z Output
OE High to High-Z Output
Output Hold from Address Change
28C64B-12
Min. Max.
120
120
120
60
0
0
50
50
0
28C64B-15
Min. Max.
150
150
150
70
0
0
50
50
0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 1. A.C. Testing Input/Output Waveform(3)
2.4 V
0.45 V
INPUT PULSE LEVELS
2.0 V
0.8 V
REFERENCE POINTS
Figure 2. A.C. Testing Load Circuit (example)
1.3V
1N914
DEVICE
UNDER
TEST
3.3K
OUT
CL = 100 pF
5096 FHD F03
CL INCLUDES JIG CAPACITANCE
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer.
(3) Input rise and fall times (10% and 90%) < 10 ns.
5096 FHD F04
5 Doc. No. 25006-0A 2/98 P-1
5 Page 
CAT28C64B
To activate the software data protection, the device must
be sent three write commands to specific addresses with
specific data (Figure 9). This sequence of commands
(along with subsequent writes) must adhere to the page
write timing specifications (Figure 11). Once this is done,
all subsequent byte or page writes to the device must be
preceded by this same set of write commands. The data
protection mechanism is activated until a deactivate
sequence is issued regardless of power on/off transi-
tions. This gives the user added inadvertent write pro-
tection on power-up in addition to the hardware protec-
tion provided.
To allow the user the ability to program the device with
an E2PROM programmer (or for testing purposes) there
is a software command sequence for deactivating the
data protection. The six step algorithm (Figure 10) will
reset the internal protection circuitry, and the device will
return to standard operating mode (Figure 12 provides
reset timing). After the sixth byte of this reset sequence
has been issued, standard byte or page writing can
commence.
Figure 11. Software Data Protection Timing
DATA
ADDRESS
AA
1555
55
0AAA
CE
WE
A0
1555
tWP
tBLC
BYTE OR
PAGE
WRITES
ENABLED
tWC
5094 FHD F13
Figure 12. Resetting Software Data Protection Timing
DATA
ADDRESS
AA
1555
55
0AAA
80
1555
AA
1555
CE
WE
ORDERING INFORMATION
Prefix Device #
Suffix
55
0AAA
20 tWC
1555
SDP
RESET
DEVICE
UNPROTECTED
5094 FHD F14
CAT 28C64B
N
I -15 T
Product
Number
Optional
Company
ID
Temperature Range
Blank = Commercial (0˚C to +70˚C)
I = Industrial (-40˚C to +85˚C)
A = Automotive (-40˚ to +105˚C)*
Tape & Reel
T: 500/Reel
Package
P: PDIP
J: SOIC (JEDEC)
K: SOIC (EIAJ)
N: PLCC
T13: TSOP (8mmx13.4mm)
Speed
12: 120ns
15: 150ns
* -40˚C to +125˚C is available upon request
Notes:
28C64B F15
(1) The device used in the above example is a CAT28C64BNI-15T (PLCC, Industrial temperature, 150 ns Access Time, Tape & Reel).
11 Doc. No. 25006-0A 2/98 P-1
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet CAT28C64B.PDF ] | |
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