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PDF M312L5720GH3-CB3 Data sheet ( Hoja de datos )
| Número de pieza | M312L5720GH3-CB3 | |
| Descripción | DDR SDRAM Registered DIMM | |
| Fabricantes | Samsung | |
| Logotipo |  |
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1GB, 2GB Registered DIMM
DDR SDRAM
DDR SDRAM Registered Module
184pin Registered Module based on 512Mb G-die
with 72-bit ECC
60 ball FBGA with Lead-Free and Halogen-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE
CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-
WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL-
OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT
GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
1 of 17
Rev. 1.0 October 2009
1 page  
1GB, 2GB Registered DIMM
DDR SDRAM
4.0 Pin Configuration (Front side/back side)
Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back
1
VREF
32
A5
62 VDDQ 93
VSS 124 VSS 154 RAS
2
DQ0
33 DQ24 63
WE
94
DQ4
125
A6
155 DQ45
3
VSS
34
VSS
64 DQ41 95
DQ5
126 DQ28 156 VDDQ
4
DQ1
35 DQ25 65
CAS
96 VDDQ 127 DQ29 157 CS0
5 DQS0 36 DQS3 66
VSS
97 DM0/DQS9 128
VDDQ
158
CS1
6
DQ2
37
A4
67 DQS5 98
DQ6
129 DM3/DQS12 159 DM5/DQS14
7
VDD
38
VDD
68 DQ42 99
DQ7
130
A3
160 VSS
8
DQ3
39
DQ26
69
DQ43
100
VSS
131 DQ30 161 DQ46
9 NC 40 DQ27 70 VDD 101 NC 132 VSS 162 DQ47
10 RESET 41
A2
71
*CS2
102
NC
133 DQ31 163 *CS3
11 VSS 42
12 DQ8 43
13 DQ9 44
14 DQS1 45
VSS
A1
CB0
CB1
72
DQ48
103
NC
134 CB4 164 VDDQ
73 DQ49 104 VDDQ 135 CB5 165 DQ52
74 VSS 105 DQ12 136 VDDQ 166 DQ53
75 *CK2 106 DQ13 137 CK0 167 *A13
15 VDDQ 46
VDD
76
*CK2
107 DM1/DQS10 138
CK0
168
VDD
16
*CK1
47 DQS8 77
VDDQ
108
VDD
139
VSS
169 DM6/DQS15
17 *CK1 48 A0 78 DQS6 109 DQ14 140 DM8/DQS17 170 DQ54
18 VSS 49 CB2 79 DQ50 110 DQ15 141 A10 171 DQ55
19 DQ10 50 VSS 80 DQ51 111 CKE1 142 CB6 172 VDDQ
20 DQ11 51 CB3 81 VSS 112 VDDQ 143 VDDQ 173 NC
21 CKE0 52
BA1
82
VDDID
113
*BA2
144
CB7
174 DQ60
22 VDDQ
KEY
83 DQ56 114 DQ20
KEY
175 DQ61
23
DQ16
53
DQ32
84
DQ57
115
A12
145
VSS
176
VSS
24 DQ17 54 VDDQ 85
VDD 116 VSS 146 DQ36 177 DM7/DQS16
25 DQS2 55 DQ33 86 DQS7 117 DQ21 147 DQ37 178 DQ62
26
VSS
56
DQS4
87
DQ58
118
A11
148
VDD
179 DQ63
27
A9
57
DQ34
88
DQ59
119 DM2/DQS11 149 DM4/DQS13 180
VDDQ
28 DQ18 58 VSS 89 VSS 120 VDD 150 DQ38 181 SA0
29
A7
59 BA0 90
NC
121 DQ22 151 DQ39 182
SA1
30 VDDQ 60 DQ35 91
31 DQ19 61 DQ40 92
SDA
SCL
122 A8 152 VSS 183 SA2
123 DQ23 153 DQ44 184 VDDSPD
Note :
1. * : These pins are not used in this module.
2. Pins 111, 158 are NC for 1row module & used for 2row module.
3. Pins 97, 107, 119, 129, 140, 149, 159, 169, 177 : DM (x8 base module) or DQS (x4 base module).
5.0 Pin Description
Pin Name
Function
Pin Name
Function
A0 ~ A12
Address input (Multiplexed)
DM0 ~ DM8 Data - in mask
BA0 ~ BA1
Bank Select Address
VDD
Power supply
(2.5V for DDR266/333, 2.6V for DDR400)
DQ0 ~ DQ63
Data input/output
VDDQ
Power Supply for DQS
(2.5V for DDR266/333, 2.6V for DDR400)
DQS0 ~ DQS17
CK0,CK0
CKE0, CKE1(for double rank)
CS0, CS1(for double rank)
Data Strobe input/output
Clock input
Clock enable input
Chip select input
VSS
VREF
VDDSPD
SDA
Ground
Power supply for reference
Serial EEPROM Power/Supply ( 2.3V to 3.6V )
Serial data I/O
RAS
Row address strobe
SCL Serial clock
CAS
Column address strobe
SA0 ~ 2 Address in EEPROM
WE
CB0 ~ CB7
Write enable
Check bit(Data-in/data-out)
VDDID
NC
VDD, VDDQ level detection
No connection
Note : VDDID defines relationship of VDD and VDDQ, and the default status of it is open (VDD=VDDQ)
5 of 17
Rev. 1.0 October 2009
5 Page 
1GB, 2GB Registered DIMM
DDR SDRAM
12.0 AC Timming Parameters & Specifications
Parameter
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay
Row precharge time
Row active to Row active delay
Write recovery time
Last data in to Read command
CL=2.0
Clock cycle time
CL=2.5
CL=3.0
Clock high level width
Clock low level width
DQS-out access time from CK/CK
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
Read Postamble
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
DQS-in low level width
Address and Control Input setup time(fast)
Address and Control Input hold time(fast)
Address and Control Input setup time(slow)
Address and Control Input hold time(slow)
Data-out high impedence time from CK/CK
Data-out low impedence time from CK/CK
Mode register set cycle time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
Control & Address input pulse width
DQ & DM input pulse width
Exit self refresh to non-Read command
Exit self refresh to read command
Refresh interval time
Output DQS valid window
Clock half period
Data hold skew factor
DQS write postamble time
Active to Read with Auto precharge
command
Autoprecharge write recovery +
Precharge time
Symbol
tRC
tRFC
tRAS
tRCD
tRP
tRRD
tWR
tWTR
tCK
tCH
tCL
tDQSCK
tAC
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPREH
tDSS
tDSH
tDQSH
tDQSL
tIS
tIH
tIS
tIH
tHZ
tLZ
tMRD
tDS
tDH
tIPW
tDIPW
tXSNR
tXSRD
tREFI
tQH
tHP
tQHS
tWPST
tRAP
tDAL
CC
(DDR400@CL=3.0)
Min Max
55
70
40 70K
15
15
10
15
2
--
6 12
5 10
0.45 0.55
0.45 0.55
-0.55
+0.55
-0.65
+0.65
- 0.4
0.9 1.1
0.4 0.6
0.72 1.28
0
0.25
0.2
0.2
0.35
0.35
0.6
0.6
0.7
0.7
-0.65
+0.65
-0.65
+0.65
10
0.4
0.4
2.2
1.75
75
200
tHP
-tQHS
tCLmin
or tCHmin
0.4
7.8
-
-
0.5
0.6
15
(tWR/tCK)
+
(tRP/tCK)
B3
(DDR333@CL=2.5)
Min Max
60
72
42 70K
18
18
12
15
1
7.5 12
6 12
--
0.45 0.55
0.45 0.55
-0.6 +0.6
-0.7 +0.7
- 0.45
0.9 1.1
0.4 0.6
0.75 1.25
0
0.25
0.2
0.2
0.35
0.35
0.75
0.75
0.8
0.8
-0.7 +0.7
-0.7 +0.7
12
0.45
0.45
2.2
1.75
75
200
tHP
-tQHS
tCLmin
or tCHmin
0.4
7.8
-
-
0.55
0.6
18
(tWR/tCK)
+
(tRP/tCK)
B0
(DDR266@CL=2.5)
Min Max
65
75
45 70K
20
20
15
15
1
10 12
7.5 12
--
0.45 0.55
0.45 0.55
-0.75
+0.75
-0.75
+0.75
- 0.5
0.9 1.1
0.4 0.6
0.75 1.25
0
0.25
0.2
0.2
0.35
0.35
0.9
0.9
1.0
1.0
-0.75
+0.75
-0.75
+0.75
15
0.5
0.5
2.2
1.75
75
200
tHP
-tQHS
tCLmin
or tCHmin
0.4
7.8
-
-
0.75
0.6
20
(tWR/tCK)
+
(tRP/tCK)
Unit Note
ns
ns
ns
ns
ns
ns
ns
tCK
ns
ns
tCK
tCK
ns
ns
ns 22
tCK
tCK
tCK
ns 13
tCK
tCK
tCK
tCK
tCK
ns 15, 17~19
ns 15, 17~19
ns 16~19
ns 16~19
ns 11
ns 11
ns
ns j, k
ns j, k
ns 18
ns 18
ns
tCK
us 14
ns 21
ns 20, 21
ns 21
tCK 12
tCK 23
11 of 17
Rev. 1.0 October 2009
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet M312L5720GH3-CB3.PDF ] | |
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