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PDF CAT25C64 Data sheet ( Hoja de datos )
| Número de pieza | CAT25C64 | |
| Descripción | 32K/64K-Bit SPI Serial CMOS E2PROM | |
| Fabricantes | Catalyst Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CAT25C64 (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
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Advance Information
CAT25C64/128
64K/128K-Bit SPI Serial CMOS E2PROM
FEATURES
s 5 MHz SPI Compatible
s 1.8 to 6.0 Volt Operation
s Hardware and Software Protection
s Zero Standby Current
s Low Power CMOS Technology
s SPI Modes (0,0)
s Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
s 1,000,000 Program/Erase Cycles
s 100 Year Data Retention
s Self-Timed Write Cycle
s 8-Pin DIP/SOIC, 16-Pin SOIC and 20-Pin TSSOP
s 64-Byte Page Write Buffer
s Block Write Protection
– Protect 1/4, 1/2 or all of E2PROM Array
The CAT25C64/128 is a 64K/128K-Bit SPI Serial CMOS
E2PROM internally organized as 8Kx8/16Kx8 bits.
Catalyst’s advanced CMOS Technology substantially
reduces device power requirements. The CAT25C64/
128 features a 64-byte page write buffer. The device
operates via the SPI bus serial interface and is enabled
though a Chip Select (CS). In addition to the Chip Select,
the clock input (SCK), data in (SI) and data out (SO) are
required to access the device. The HOLD pin may be
used to suspend any serial communication without
resetting the serial sequence. The CAT25C64/128 is
designed with software and hardware write protection
features including Block write protection. The device is
available in 8-pin DIP, 8-pin SOIC, 16-pin SOIC and 20-
pin TSSOP packages.
PIN CONFIGURATION
BLOCK DIAGRAM
SOIC Package (S) SOIC Package (S16) TSSOP Package (U20)
CS
SO
WP
VSS
1
2
3
4
8
7
VCC
HOLD
CS
1
6 SCK
SO 2
5 SI
NC 3
NC 4
DIP Package (P)
NC 5
NC 6
CS 1
SO 2
8 VCC
7 HOLD
WP 7
VSS 8
WP
VSS
3
4
6 SCK
5 SI
16 VCC NC 1
15 HOLD CS 2
14
NC
SO 3
SO 4
13 NC NC 5
12 NC NC 6
WP 7
11 NC VSS 8
10 SCK NC 9
9 SI
NC 10
PIN FUNCTIONS
Pin Name
Function
SO
SCK
Serial Data Output
Serial Clock
20 NC
19 VCC
18 HOLD
17 HOLD
16 NC
15 NC
14 SCK
13 SI
12 NC
11 NC
WORD ADDRESS
BUFFERS
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
SO
SI
CS
WP
HOLD
SCK
I/O
CONTROL
SPI
CONTROL
LOGIC
XDEC
E2PROM
ARRAY
WP Write Protect
VCC +1.8V to +6.0V Power Supply
BLOCK
PROTECT
LOGIC
VSS Ground
CS Chip Select
DATA IN
STORAGE
SI
HOLD
NC
Serial Data Input
Suspends Serial Input
No Connect
STATUS
REGISTER
HIGH VOLTAGE/
TIMING CONTROL
25C128 F02
© 1999 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc No. 25069-00 6/99 SPI-1
1 page  
Advance Information
CAT25C64/128
STATUS REGISTER
The Status Register indicates the status of the device.
The RDY (Ready) bit indicates whether the CAT25C64/
128 is busy with a write operation. When set to 1 a write
cycle is in progress and when set to 0 the device
indicates it is ready. This bit is read only.
The WEL (Write Enable) bit indicates the status of the
write enable latch . When set to 1, the device is in a Write
Enable state and when set to 0 the device is in a Write
Disable state. The WEL bit can only be set by the WREN
instruction and can be reset by the WRDI instruction.
The BP0 and BP1 (Block Protect) bits indicate which
blocks are currently protected. These bits are set by the
user issuing the WRSR instruction. The user is allowed
to protect quarter of the memory, half of the memory or
the entire memory by setting these bits. Once protected
the user may only read from the protected portion of the
STATUS REGISTER
7654
WPEN
X
X
X
array. These bits are non-volatile.
The WPEN (Write Protect Enable) is an enable bit for the
WP pin. The WP pin and WPEN bit in the status register
control the programmable hardware write protect fea-
ture. Hardware write protection is enabled when WP is
low and WPEN bit is set to high. The user cannot write
to the status register (including the block protect bits and
the WPEN bit) and the block protected sections in the
memory array when the chip is hardware write pro-
tected. Only the sections of the memory array that are
not block protected can be written. Hardware write
protection is disabled when either WP pin is high or the
WPEN bit is zero.
3210
BP1
BP0
WEL
RDY
BLOCK PROTECTION BITS
Status Register Bits
BP1 BP0
00
01
10
11
Array Address
Protected
None
25C128: 3000-3FFF
25C64:1800-1FFF
25C128: 2000-3FFF
25C64:1000-1FFF
25C128: 0000-3FFF
25C64:1000-1FFF
Protection
No Protection
Quarter Array Protection
Half Array Protection
Full Array Protection
WRITE PROTECT ENABLE OPERATION
WPEN
0
0
1
1
X
X
WP
X
X
Low
Low
High
High
WEL
0
1
0
1
0
1
Protected
Blocks
Protected
Protected
Protected
Protected
Protected
Protected
Unprotected
Blocks
Protected
Writable
Protected
Writable
Protected
Writable
Status
Register
Protected
Writable
Protected
Protected
Protected
Writable
5 Doc No. 25069-00 6/99 SPI-1
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet CAT25C64.PDF ] | |
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